Display device

Abstract

A display device is disclosed by the present disclosure. The display device includes: a display panel having a plurality of sub-pixels, the sub-pixels being connected to a plurality of scan lines and a plurality of data lines; and a gate driver for supplying a scan signal at a high level to the plurality of scan lines. The gate driver may include: a first gate driver for outputting a carry signal at a low level; a second gate driver for outputting the scan signal at the high level based on the carry signal; a first clock signal line connected to the first and the second gate driver; and a second clock signal line connected to the first and the second gate driver. Accordingly, the gate driver can generate a high-level scan signal based on the low-level carry signal from the first gate driver.

The invention claimed is: 
     
       1. A display device comprising:
 a display panel having a plurality of sub-pixels thereon, the sub-pixels being connected to a plurality of scan lines and a plurality of data lines; and 
 a gate driver for supplying a scan signal at a high level to the plurality of scan lines, 
 wherein the gate driver comprises: 
 a first gate driver for outputting a carry signal at a low level and including a plurality of cascaded first stages; 
 a second gate driver for outputting the scan signal at the high level based on the carry signal and including a plurality of second stages each comprising a second output terminal connected to a respective one of the plurality of scan lines; 
 a first clock signal line connected to the first gate driver and the second gate driver; and 
 a second clock signal line connected to the first gate driver and the second gate driver, 
 wherein the display device comprises a start signal line connected to a top first stage among the plurality of first stages and a top second stage among the plurality of second stages, each of the plurality of first stages other than the top first stage is connected to a first output terminal of a previous one of the plurality of first stages, and each of the plurality of second stages other than the top second stage is connected to the first output terminal of the previous one of the plurality of first stages, 
 wherein each of the plurality of first stages comprises: 
 a first transistor having a gate electrode connected to a Q node, and a source electrode and a drain electrode connected between the first clock signal line and the first output terminal; 
 a second transistor having a gate electrode connected to a QB node and a drain electrode connected to the first output terminal; 
 a third transistor having a gate electrode connected to the second clock signal line and a source electrode and a drain electrode connected between the first output terminal of the previous first stage and a Q 2  node; 
 a fourth transistor having a source electrode or a drain electrode connected to the Q 2  node: 
 a fifth transistor having a gate electrode connected to the QB node; 
 a sixth transistor having a gate electrode connected to the second clock signal line and a drain electrode connected to the QB node; and 
 a seventh transistor having a gate electrode connected to the Q 2  node and the Q node. 
 
     
     
       2. The display device of  claim 1 , wherein the carry signal output from the first stage in an nth row among the plurality of first stages is transmitted to the first stage in an (n+1)th row among the plurality of first stages and the second stage in the (n+1)th row among the plurality of second stages. 
     
     
       3. The display device of  claim 1 , wherein when the carry signal is output from the previous first stage and a clock signal at a low level is provided from the second clock signal line, the third transistor is turned on to transmit the carry signal to the Q node, and the first transistor is turned on by a voltage at the Q node to output a clock signal from the first clock signal line to the first output terminal. 
     
     
       4. The display device of  claim 1 , wherein each of the plurality of second stages comprises:
 an eighth transistor having a gate electrode connected to a QBN node, and a source electrode and a drain electrode connected between the second clock signal line and the second output terminal; 
 a ninth transistor having a gate electrode connected to a QN node and a drain electrode connected to the second output terminal; 
 a tenth transistor having a gate electrode connected to the second clock signal line, and a source electrode and a drain electrode connected between the first output terminal of the previous first stage and the QBN node; 
 an eleventh transistor having a source electrode and a drain electrode connected between the QBN node and a gate-high line from which a gate-high voltage is supplied; 
 a twelfth transistor having a gate electrode connected to the QBN node, and a source electrode and a drain electrode connected between the gate-high line and a QN 2  node; 
 a thirteenth transistor having a drain electrode connected to the QN 2  node; and 
 a fourteenth transistor having a gate electrode connected to the QN node, and a source electrode and a drain electrode connected to between the QBN node and a gate-low line from which a gate-low voltage is supplied. 
 
     
     
       5. The display device of  claim 4 , wherein when the carry signal is output from the previous first stage and a clock signal at a low level is provided from the second clock signal line, the tenth transistor transmits the carry signal to the QBN node, and the twelfth transistor is turned on by the carry signal to transmit the gate-high voltage to the QN node. 
     
     
       6. The display device of  claim 5 , wherein when the gate-high voltage is transmitted to the QN node, the fourteenth transistor is turned on to transmit the gate-low voltage to the QBN node, and the eighth transistor is turned on by a voltage at the QBN node to output the clock signal from the second clock signal line to the second output terminal. 
     
     
       7. The display device of  claim 4 , wherein each of the plurality of first stages further comprises:
 a first capacitor connected between the Q node and the first output terminal; and 
 a second capacitor connected to the QB node, 
 wherein each of the plurality of second stages comprises: 
 a third capacitor connected between the QN node and the second output terminal, 
 wherein the first transistor remains turn on by the first capacitor when the carry signal is output, and 
 wherein the ninth transistor remains turned off by the third capacitor when the scan signal is output. 
 
     
     
       8. The display device of  claim 1 , wherein each of the plurality of sub-pixels comprises:
 a driving transistor having a gate electrode connected to a first node, a source electrode connected to a second node, and a drain electrode connected to a third node; 
 a first pixel transistor having a source electrode and a drain electrode connected between the first node and a third node; and 
 a second pixel transistor having a gate electrode connected to the plurality of scan lines, and a source electrode and a drain electrode connected between the second node and the plurality of data lines, 
 wherein the second pixel transistor is an n-type oxide semiconductor transistor that is turned on by the high-level scan signal supplied from the plurality of scan lines. 
 
     
     
       9. A gate driver for controlling an n-type transistor with the driving timing for controlling a p-type transistor comprising:
 a first gate driver for outputting a carry signal at a low level and including a plurality of cascaded first stages; 
 a second gate driver for outputting a scan signal at a high level based on the carry signal and including a plurality of second stages each comprising a second output terminal; 
 a first clock signal line connected to the first gate driver and the second gate driver; and 
 a second clock signal line connected to the first gate driver and the second gate driver, 
 wherein the gate driver comprises a start signal line connected to a top first stage among the plurality of first stages and a top second stage among the plurality of second stages, each of the plurality of first stages other than the top first stage is connected to a first output terminal of a previous one of the plurality of first stages, and each of the plurality of second stages other than the top second stage is connected to the first output terminal of the previous one of the plurality of first stages, 
 wherein each of the plurality of first stages comprises: 
 a first transistor having a gate electrode connected to a Q node, and a source electrode and a drain electrode connected between the first clock signal line and the first output terminal; 
 a second transistor having a gate electrode connected to a QB node and a drain electrode connected to the first output terminal; 
 a third transistor having a gate electrode connected to the second clock signal line and a source electrode and a drain electrode connected between the first output terminal of the previous first stage and a Q 2  node; 
 a fourth transistor having a source electrode or a drain electrode connected to the Q 2  node; 
 a fifth transistor having a gate electrode connected to the QB node; 
 a sixth transistor having a gate electrode connected to the second clock signal line and a drain electrode connected to the QB node; and 
 a seventh transistor having a gate electrode connected to the Q 2  node and the Q node.