Memory device related to performing a program operation on memory cells

Abstract

Provided herein is a memory device for performing a program operation on memory cells. The memory device include a plurality of memory cells configured to store data, a voltage generator configured to apply program voltages to a word line coupled to the plurality of memory cells during a program operation in which the plurality of memory cells are programmed to a plurality of program states, a cell speed determiner configured to determine a program speed of the plurality of memory cells depending on a number of pulses for the program voltages applied to the word line while the program operation is being performed, and a program manager configured to change a condition for remaining program operations depending on the program speed determined by the cell speed determiner.

What is claimed is: 
     
       1. A memory device, comprising:
 a plurality of memory cells configured to store data; 
 a voltage generator configured to apply program voltages to a word line coupled to the plurality of memory cells during a program operation in which the plurality of memory cells are programmed to a plurality of program states; 
 a cell speed determiner configured to determine a program speed of the plurality of memory cells depending on a number of pulses for the program voltages applied to the word line while the program operation is being performed; and 
 a program manager configured to change a condition for remaining program operations depending on the program speed determined by the cell speed determiner, 
 wherein the program manager is configured to: 
 generate an operation code so that at least one of a level of each program voltage, an active time of the program voltage, a level of a step voltage for the program voltage, at least one of offsets for the program voltage that are included in the condition for the remaining program operations, and a verify voltage is controlled depending on the program speed determined by the cell speed determiner, and 
 transmit the operation code to the voltage generator. 
 
     
     
       2. The memory device according to  claim 1 , further comprising:
 page buffers configured to store verification data depending on one of voltages and currents of a plurality of bit lines coupled to the plurality of memory cells during a verify operation performed in the program operation. 
 
     
     
       3. The memory device according to  claim 2 , further comprising:
 a sensing circuit configured to, when a number of fail bits included in the verification data is greater than an allowable number of fail bits, output a fail signal, and when the number of fail bits is less than or equal to the allowable number of fail bits, output a pass signal. 
 
     
     
       4. The memory device according to  claim 1 , wherein the cell speed determiner is configured to:
 compare a pulse count of the program voltages used to perform programming to a reference state selected from among target program states of the plurality of memory cells with a reference pulse count, and 
 output a determination result as a result of the comparison. 
 
     
     
       5. The memory device according to  claim 4 , wherein the cell speed determiner is configured to, when the pulse count is equal to the reference pulse count,
 determine the program speed of the plurality of memory cells to be normal, and 
 output the determination result including information about a normal program speed. 
 
     
     
       6. The memory device according to  claim 4 , wherein the cell speed determiner is configured to, when the pulse count is less than the reference pulse count,
 determine the program speed of the plurality of memory cells to be fast, and 
 output the determination result including information about a fast program speed. 
 
     
     
       7. The memory device according to  claim 4 , wherein the cell speed determiner is configured to, when the pulse count is greater than the reference pulse count,
 determine the program speed of the plurality of memory cells to be slow, and 
 output the determination result including information about a slow program speed. 
 
     
     
       8. The memory device according to  claim 1 , wherein:
 each program voltage is set to a voltage for increasing threshold voltages of memory cells selected from among the plurality of memory cells, 
 the active time of the program voltage is set to a time during which the program voltage is applied to the word line to increase the threshold voltages of the selected memory cells, 
 the step voltage is set to a voltage difference between a previous program voltage and a next program voltage when the program voltage is increased, and 
 the offsets are used to decrease or increase levels of a part or all of program voltages during the remaining program operations. 
 
     
     
       9. The memory device according to  claim 1 , wherein the program manager is configured to, when the program speed is determined to be normal, generate the operation code so that the level of each program voltage, the active time of the program voltage, and the level of the step voltage are maintained at initially set values. 
     
     
       10. The memory device according to  claim 1 , wherein the program manager is configured to perform at least one of, when the program speed is determined to be fast,
 generate the operation code so that a minus offset is applied to each program voltage, 
 generate the operation code so that at least one of the active time of the program voltage and the level of the step voltage is decreased from an initially set value, and 
 generate the operation code so that, after the program voltage is applied to the word line, the minus offset is applied to the program voltage. 
 
     
     
       11. The memory device according to  claim 1 , wherein the program manager is configured to perform at least one of, when the program speed is determined to be slow,
 generate the operation code so that a plus offset is applied to each program voltage, 
 generate the operation code so that at least one of the active time of the program voltage and the level of the step voltage is increased from an initially set value, and 
 generate the operation code so that, after the program voltage is applied to the word line, the plus offset is applied to the program voltage. 
 
     
     
       12. A memory device, comprising:
 a plurality of memory cells included in a selected page; 
 a control logic circuit configured to determine a program speed at a time at which memory cells selected from among the plurality of memory cells are programmed to a reference state, among different target program states, while the plurality of memory cells are being programmed to the different target program states, and to change a condition for a program operation based on the determined program speed; and 
 a voltage generator configured to output program voltages so that remaining program operations are performed under control of the control logic circuit, 
 wherein the control logic circuit is configured to control a condition of at least one of a level of each program voltage, a level of a step voltage, an active time during which the program voltage is applied to a word line, an offset for the program voltage, and a verify voltage depending on the program speed of the memory cells programmed to the reference state during the program operation, and to generate and output an operation code to which the controlled condition is applied during the remaining program operations. 
 
     
     
       13. The memory device according to  claim 12 , wherein the reference state is set among the target program states except a lowest program state and a highest program state. 
     
     
       14. The memory device according to  claim 12 , wherein the control logic circuit is configured to, when the program speed of the selected memory cells programmed to the reference state is determined to be a normal program speed, maintain the program voltage, the step voltage, and the active time of the program operation. 
     
     
       15. The memory device according to  claim 12 , wherein the control logic circuit is configured to, when the program speed of the selected memory cells programmed to the reference state is determined to be a fast program speed higher than a normal program speed, control the voltage generator so that the remaining program operations are performed by, at least one of, applying a minus offset to the program voltage, decreasing the level of the step voltage from a previous level, and by decreasing the active time. 
     
     
       16. The memory device according to  claim 12 , wherein the control logic circuit is configured to, when the program speed of the selected memory cells programmed to the reference state is determined to be a slow program speed lower than a normal program speed, control the voltage generator so that the remaining program operations are performed by, at least one of, applying a plus offset to the program voltage, increasing the level of the step voltage from a previous level, and increasing the active time.