Reduced semiconductor wafer bow and warpage

Abstract

Forming an integrated circuit, for example by first, concurrently forming a first front end of line (FEOL) layer having a first thickness and a surface contacting or facing a semiconductor substrate frontside and a second FEOL layer, having a second thickness and including a same material as the first FEOL layer and having a surface contacting or facing a semiconductor substrate backside, and second, processing the second FEOL layer to reduce the second thickness.

What is claimed is: 
     
       1. A method of forming an integrated circuit, comprising:
 concurrently forming a first front end of line (FEOL) layer at a frontside of a semiconductor substrate and a second FEOL layer at a backside of the semiconductor substrate opposite the frontside, wherein the first and second FEOL layers include a same material, and wherein the second FEOL layer has a first thickness; and 
 removing at least a portion of the second FEOL layer such that the second FEOL layer has a second thickness less than the first thickness as a result of removing at least the portion of the second FEOL layer. 
 
     
     
       2. The method of  claim 1 , wherein the first FEOL layer includes a nitride layer. 
     
     
       3. The method of  claim 2 , further including:
 forming a first nitride layer mask by patterning and etching the first FEOL layer; and 
 etching a deep trench through the first nitride layer mask. 
 
     
     
       4. The method of  claim 3 , wherein the deep trench has a depth between 0.4 μm and 150 μm. 
     
     
       5. The method of  claim 3 , wherein the deep trench has a depth between 20 μm and 150 μm. 
     
     
       6. The method of  claim 3 , wherein:
 the semiconductor substrate is a portion of a semiconductor wafer; and 
 the deep trench is a first deep trench in a plurality of deep trenches formed in at least 0.1% or greater of a frontside of the semiconductor wafer. 
 
     
     
       7. The method of  claim 3 , further including:
 forming a polysilicon material within the deep trench. 
 
     
     
       8. The method of  claim 7 , wherein forming the polysilicon material within the deep trench concurrently forms a backside polysilicon layer at the backside of the semiconductor substrate, the backside polysilicon layer having a third thickness, and wherein the method further includes removing at least a portion of the backside polysilicon layer such that the backside polysilicon layer has a fourth thickness less than the third thickness as a result of removing at least the portion of the backside polysilicon layer. 
     
     
       9. The method of  claim 8 , wherein removing at least the portion of the backside polysilicon layer includes completely removing the backside polysilicon layer. 
     
     
       10. The method of  claim 8 , wherein the backside the fourth thickness is greater than zero. 
     
     
       11. The method of  claim 1 , wherein removing at least the portion of the second FEOL layer includes completely removing the second FEOL layer. 
     
     
       12. The method of  claim 1 , wherein the second thickness is greater than zero. 
     
     
       13. The method of  claim 1 , wherein the first FEOL layer includes a silicon nitride layer, a silicon oxynitride layer, or both. 
     
     
       14. The method of  claim 1 , wherein the forming a first FEOL layer includes forming the first FEOL layer as part of a LOCOS loop. 
     
     
       15. The method of  claim 1 , wherein the forming a first FEOL layer includes forming the first FEOL layer as part of an offset layer. 
     
     
       16. The method of  claim 1 , wherein the forming a first FEOL layer includes forming the first FEOL layer as part of a sidewall spacer layer. 
     
     
       17. The method of  claim 1 , wherein the first FEOL layer includes a polysilicon layer.