Shared components in fuse match logic

Abstract

A memory device includes a memory cell array and a set of fuse banks including a common fuse bank storing common bit information corresponding to a plurality of defective memory cells in the memory cell array. The memory device including a plurality of match sub-circuits corresponding to respective defective memory cells of the plurality of defective memory cells. Each match sub-circuit can be configured to provide a determination of whether a memory cell address of a memory cell of the memory cell array matches an address of the respective defective memory cell. The plurality of match sub-circuit can include a shared common bit-processing circuit that is configured to receive common bit-by-bit results of a comparison between a portion of the memory cell address and the common bit information. The common bit-processing circuit can determine whether the common bit information matches the portion of the memory cell address.

We claim: 
     
       1. A memory device, comprising:
 a memory cell array; 
 a set of fuse banks including a common fuse bank storing common bit information corresponding to a plurality of defective memory cells in the memory cell array; and 
 a repair circuit including a plurality of match sub-circuits corresponding to respective defective memory cells of the plurality of defective memory cells, each match sub-circuit configured to provide a determination of whether a memory cell address of a memory cell of the memory cell array matches an address of the respective defective memory cell, 
 wherein the plurality of match sub-circuits include a shared common bit-processing circuit that is configured to receive common bit-by-bit results of a comparison between a portion of the memory cell address and the common bit information and determine whether the common bit information matches the portion of the memory cell address. 
 
     
     
       2. The memory device of  claim 1 , wherein the plurality of defective memory cells includes a first defective memory cell and a second defective memory cell, and
 wherein the plurality of match sub-circuits includes a first match sub-circuit to provide a first determination of whether the memory cell address matches a first address of the first defective memory cell and a second match sub-circuit to provide a second determination of whether the memory cell address matches a second address of the second defective memory cell. 
 
     
     
       3. The memory device of  claim 2 , wherein the common bit information corresponds to X least significant bits (LSBs) of the first address and the second address, where X is an integer greater than zero and less than a total number of address bits of the first defective memory cell or the second defective memory cell. 
     
     
       4. The memory device of  claim 2 , wherein the set of fuse banks further includes a first fuse bank storing first bit information corresponding to the first defective memory cell, and a second fuse bank storing second bit information corresponding to the second defective memory cell. 
     
     
       5. The memory device of  claim 4 , wherein the repair circuit includes a bit compare circuit configured to generate the common bit-by-bit results, first bit-by-bit results based on a comparison between a first portion of the memory cell address and the first bit information, and second bit-by-bit results based on a comparison between the first portion of the memory cell address and the second bit information. 
     
     
       6. The memory device of  claim 5 , wherein the first match sub-circuit includes a first bit-processing circuit that is exclusive to the first match sub-circuit and configured to process the first bit-by-bit results, and
 wherein the second match sub-circuit includes a second bit-processing circuit that is exclusive to the second match sub-circuit and configured to process the second bit-by-bit results. 
 
     
     
       7. The memory device of  claim 4 , wherein the common bit information and the first bit information represent the first address, and
 wherein the common bit information and the second bit information represent the second address. 
 
     
     
       8. The memory device of  claim 4 , wherein the first bit information, the second bit information, and the common bit information correspond to row addresses. 
     
     
       9. The memory device of  claim 4 , wherein the first bit information, the second bit information, and the common bit information correspond to column addresses. 
     
     
       10. The memory device of  claim 4 , wherein the first bit information, the second bit information, and the common bit information are respectively programmed into the first fuse bank, the second fuse bank, and the common fuse bank using at least one of fuses, latches, or anti-fuses. 
     
     
       11. The memory device of  claim 2 , wherein, when the first determination indicates that the memory cell address matches the first address, the first match sub-circuit outputs a first repair signal, and
 wherein, when the second determination indicates that the memory cell address matches the second address, the second match sub-circuit outputs a second repair signal. 
 
     
     
       12. The memory device of  claim 11 , wherein the memory device is configured to direct memory operations corresponding to the memory cell to a first redundant memory cell of the memory cell array instead of the first defective memory cell based on the first repair signal and/or to direct the memory operations corresponding to the memory cell to a second redundant cell of the memory cell array instead of the second defective memory cell based on the second repair signal. 
     
     
       13. The memory device of  claim 5 , wherein the bit compare circuit includes XNOR gates, and
 wherein the common bit-by-bit results, the first bit-by-bit results, and the second bit-by-bit results are based on comparisons using the XNOR gates. 
 
     
     
       14. The memory device of  claim 1 , wherein the shared common bit-processing circuit includes NAND gates that receive and compare the common bit-by-bit results. 
     
     
       15. A method, comprising:
 storing common bit information corresponding to a first defective memory cell of a memory array and a second defective memory cell of the memory array; 
 providing a first determination of whether a memory cell address used for memory operations on a memory cell of the memory array corresponds to a first address of the first defective memory cell; 
 providing a second determination of whether the memory cell address corresponds to a second address of the second defective memory cell; 
 receiving common bit-by-bit results based on a comparison between a portion of the memory cell address and the common bit information; and 
 determining whether the common bit information matches the portion of the memory cell address. 
 
     
     
       16. The method of  claim 15 , wherein the common bit information corresponds to X least significant bits (LSBs) of the first address and the second address, where X is an integer greater than zero and less than a total number of address bits of the first defective memory cell or the second defective memory cell. 
     
     
       17. The method of  claim 15 , further comprising:
 storing first bit information corresponding to the first defective memory cell in a first fuse bank; 
 storing second bit information corresponding to the second defective memory cell in a second fuse bank; 
 generating the common bit-by-bit results; 
 generating first bit-by-bit results based on a comparison between a first portion of the memory cell address and the first bit information; and 
 generating second bit-by-bit results based on a comparison between the first portion of the memory cell address and the second bit information. 
 
     
     
       18. The method of  claim 15 , further comprising:
 providing a first repair signal when the first determination indicates that the memory cell address matches the first address, the first repair signal to direct the memory operations corresponding to the memory cell to a first redundant memory cell of the memory cell array instead of the first defective memory cell; and 
 providing a second repair signal when the second determination indicates that the memory cell address matches the second address, the second repair signal to direct the memory operations corresponding to the memory cell to a second redundant memory cell of the memory cell array instead of the second defective memory cell. 
 
     
     
       19. A memory device, comprising:
 a memory array including a plurality of memory cells; 
 a set of fuse banks including a first fuse bank corresponding to a first defective memory cell, a second fuse bank corresponding to a second defective memory cell, and a third fuse bank corresponding to both the first defective memory cell and the second defective memory cell; and 
 a repair circuit operatively coupled to the memory array and the set of fuse banks and configured to generate bit-by-bit results of comparisons between at least a portion of an address for memory operations and bit information stored in at least one of the first fuse bank, the second fuse bank, or the third fuse bank, the repair circuit including a first match sub-circuit to provide a first determination of whether the address for memory operations corresponds to the first defective memory cell based on a first portion of the bit-by-bit results and a second match sub-circuit to provide a second determination of whether the address for memory operations corresponds to the second defective memory cell based on a second portion of the bit-by-bit results, the first portion of the bit-by-bit results and the second portion of the bit-by-bit results including bit-by-bit results that are common to both the first portion and the second portion, 
 wherein the first match sub-circuit and the second match sub-circuit include a common sub-circuit that is configured to receive and compare the common bit-by-bit results, the common bit-by-bit results corresponding to the third fuse bank. 
 
     
     
       20. The memory device of  claim 19 , wherein each of the first fuse bank and the third fuse bank stores a portion of an address corresponding to the first defective memory cell of the plurality of memory cells, and
 wherein each of the second fuse bank and the third fuse bank stores a portion of an address corresponding to a second defective memory cell of the plurality of memory cells.