Transistor structure, gate driving circuit, driving method thereof, and display panel

Abstract

The transistor structure includes a transistor and a plurality of gate lines electrically connected to the transistor, wherein the transistor includes a semiconductor layer and a source and a drain that are disposed on the semiconductor layer, the source is connected to a source region of the semiconductor layer, and the drain is connected to a drain region of the semiconductor layer; and the transistor further includes a plurality of gates disposed corresponding to a channel region of the semiconductor layer, wherein the plurality of gates are spaced in a length direction of the source and the drain, and the plurality of gates are connected to the plurality of gate lines in a one-to-one correspondence. The technical solution of the present application can compensate and adjust the transistor after a working environment temperature changes, to avoid abnormal display.

What is claimed is: 
     
       1. A transistor structure, comprising:
 a transistor and a plurality of gate lines electrically connected to the transistor, wherein the transistor comprises a semiconductor layer and a source and a drain that are disposed on the semiconductor layer, the source is connected to a source region of the semiconductor layer, and the drain is connected to a drain region of the semiconductor layer; and 
 a plurality of gates disposed corresponding to a channel region of the semiconductor layer, wherein the plurality of gates are spaced in a length direction of the source and the drain, and the plurality of gates are connected to the plurality of gate lines in a one-to-one correspondence; 
 wherein the drain comprises a first line segment, a second line segment, and a connection line segment, the first line segment, the connection line segment, and the second line segment are sequentially connected to form a U-shaped line, and the source is disposed between the first line segment and the second line segment at intervals; 
 wherein a length of the first line segment is equal to a length of the second line segment, and a distance between the source and the first line segment is equal to a distance between the source and the second line segment. 
 
     
     
       2. The transistor structure according to  claim 1 , wherein a plurality of transistors are sequentially arranged in a length direction perpendicular to the source. 
     
     
       3. The transistor structure according to  claim 2 , wherein a first line segment of a drain of one of two adjacent transistors and a second line segment of a drain of another of the two adjacent transistors are a same line segment. 
     
     
       4. The transistor structure according to  claim 1 , wherein there are at least two adjacent transistors in a length direction perpendicular to the source, and the two adjacent transistors are distributed at intervals; and the transistor structure further comprises a plurality of interval gate lines, wherein the interval gate line is disposed between the transistors distributed at intervals, and the interval gate line connects gates of the adjacent transistors. 
     
     
       5. The transistor structure according to  claim 1 , wherein the semiconductor layer comprises at least one metal oxide layer. 
     
     
       6. A gate driving circuit comprising a pull-up control module, a pull-up module, a pull-down control module, and a pull-down module, wherein the pull-up control module is configured to receive an input signal, the pull-up module is configured to receive a clock signal, and the pull-up control module and the pull-up module comprise at least one transistor structure, comprising a transistor and a plurality of gate lines electrically connected to the transistor, wherein the transistor comprises a semiconductor layer and a source and a drain that are disposed on the semiconductor layer, the source is connected to a source region of the semiconductor layer, and the drain is connected to a drain region of the semiconductor layer;
 wherein the transistor further comprises a plurality of gates disposed corresponding to a channel region of the semiconductor layer, wherein the plurality of gates are spaced in a length direction of the source and the drain, and the plurality of gates are connected to the plurality of gate lines in a one-to-one correspondence; 
 wherein the drain comprises a first line segment, a second line segment, and a connection line segment, the first line segment, the connection line segment, and the second line segment are sequentially connected to form a U-shaped line, and the source is disposed between the first line segment and the second line segment at intervals; 
 wherein a length of the first line segment is equal to a length of the second line segment, and a distance between the source and the first line segment is equal to a distance between the source and the second line segment. 
 
     
     
       7. The gate driving circuit according to  claim 6 , wherein a plurality of transistors are sequentially arranged in a length direction perpendicular to the source. 
     
     
       8. The gate driving circuit according to  claim 7 , wherein a first line segment of a drain of one of two adjacent transistors and a second line segment of a drain of another of the two adjacent transistors are a same line segment. 
     
     
       9. The gate driving circuit according to  claim 6 , wherein there are at least two adjacent transistors in a length direction perpendicular to the source, and the two adjacent transistors are distributed at intervals; and the transistor structure further comprises a plurality of interval gate lines, wherein the interval gate line is disposed between the transistors distributed at intervals, and the interval gate line connects gates of the adjacent transistors. 
     
     
       10. The gate driving circuit according to  claim 6 , wherein the semiconductor layer comprises at least one metal oxide layer. 
     
     
       11. A driving method of a gate driving circuit, the gate driving circuit including: a transistor and a plurality of gate lines electrically connected to the transistor, wherein the transistor comprises a semiconductor layer and a source and a drain that are disposed on the semiconductor layer, the source is connected to a source region of the semiconductor layer, and the drain is connected to a drain region of the semiconductor layer; and a plurality of gates disposed corresponding to a channel region of the semiconductor layer, wherein the plurality of gates are spaced in a length direction of the source and the drain, and the plurality of gates are connected to the plurality of gate lines in a one-to-one correspondence; wherein the drain comprises a first line segment, a second line segment, and a connection line segment, the first line segment, the connection line segment, and the second line segment are sequentially connected to form a U-shaped line, and the source is disposed between the first line segment and the second line segment at intervals; wherein a length of the first line segment is equal to a length of the second line segment, and a distance between the source and the first line segment is equal to a distance between the source and the second line segment;
 wherein the driving method of the gate driving circuit comprises:
 detecting an environment temperature of the gate driving circuit; 
 determining a predetermined starting quantity of gates based on the environment temperature; and 
 inputting gate signals to the predetermined starting quantity of gates by using a predetermined starting quantity of gate lines, and controlling on or off of the transistor structure. 
 
 
     
     
       12. The driving method of a gate driving circuit according to  claim 11 , wherein the predetermined starting quantity of gate lines is negatively correlated with the environment temperature.