Semiconductor memory device with defect detection capability

Abstract

According to various embodiments, a semiconductor memory device includes a substrate that includes a memory cell region and a test region. The semiconductor memory device further includes an active pattern on the memory cell region, a source/drain pattern on the active pattern, a dummy pattern on the test region, a first gate electrode on the dummy pattern, a first common contact, and a first wiring layer. The first wiring layer includes a first test line electrically connected to the first common contact. The first common contact includes a first contact pattern in contact with the dummy pattern, and a first gate contact connected to the first gate electrode. The first gate contact includes a body and a protrusion part. A lowermost level of a top surface of the active pattern is lower than a lowermost level of a top surface of the dummy pattern.

What is claimed is: 
     
       1. A semiconductor memory device, comprising:
 a substrate that comprises a memory cell region and a test region; 
 an active pattern on the memory cell region; 
 a source/drain pattern on the active pattern; 
 a dummy pattern on the test region; 
 a first gate electrode that extends in a first direction on the dummy pattern; 
 a first common contact in contact with the dummy pattern and the first gate electrode; and 
 a first wiring layer on the first common contact, 
 wherein the first wiring layer comprises a first test line electrically connected to the first common contact, 
 wherein the first common contact comprises:
 a first contact pattern in contact with the dummy pattern; and 
 a first gate contact electrically connected to the first gate electrode, 
 
 wherein the first gate contact comprises:
 a body part coupled to the first gate electrode; and 
 a protrusion part that extends from the body part and into the first contact pattern, and 
 
 wherein a lowermost level of a top surface of the active pattern is lower than a lowermost level of a top surface of the dummy pattern. 
 
     
     
       2. The semiconductor memory device of  claim 1 , wherein:
 the protrusion part vertically overlaps the first contact pattern, and 
 the body part is horizontally offset from the first contact pattern. 
 
     
     
       3. The semiconductor memory device of  claim 1 , wherein a top surface of the body part is coplanar with a top surface of the first contact pattern. 
     
     
       4. The semiconductor memory device of  claim 1 , wherein:
 the first contact pattern comprises a connection part and a recess part other than the connection part; 
 the connection part is in contact with the protrusion part; and 
 a top surface of the recess part is lower than a top surface of the connection part. 
 
     
     
       5. The semiconductor memory device of  claim 1 , further comprising:
 a second gate electrode spaced apart from the first gate electrode in a second direction that intersects the first direction; and 
 a second common contact spaced apart in the first direction from the first common contact, 
 wherein the second common contact comprises:
 a second contact pattern that contacts the dummy pattern and extends in the first direction; and 
 a second gate contact electrically connected to the second gate electrode. 
 
 
     
     
       6. The semiconductor memory device of  claim 5 , wherein the first wiring layer further comprises a second test line electrically connected to the second common contact,
 wherein a voltage applied to the second test line is different from a voltage applied to the first test line. 
 
     
     
       7. The semiconductor memory device of  claim 1 , further comprising a second wiring layer on the first wiring layer,
 wherein the second wiring layer is horizontally offset from the first test line. 
 
     
     
       8. The semiconductor memory device of  claim 1 , further comprising a first via between the first test line and the first common contact,
 wherein the first via vertically overlaps the first contact pattern. 
 
     
     
       9. The semiconductor memory device of  claim 1 , further comprising a first via between the first test line and the first common contact,
 wherein the first via is horizontally offset from the first contact pattern. 
 
     
     
       10. The semiconductor memory device of  claim 1 , wherein the first gate electrode is disposed between dielectric patterns. 
     
     
       11. A semiconductor memory device, comprising:
 a memory cell region and a test region on a substrate; 
 a dummy pattern on the test region; 
 a first gate electrode that extends in a first direction on the dummy pattern; 
 a first common contact in contact with the dummy pattern and the first gate electrode; 
 a second gate electrode spaced apart from the first gate electrode in a second direction that intersects the first direction; 
 a second common contact spaced apart in the first direction from the first common contact; and 
 a first wiring layer provided on and coupled to the first and second common contacts, 
 wherein the first wiring layer comprises a first test line and a second test line that extend in the second direction, the first and second test lines being respectively electrically connected to the first and second common contacts, 
 wherein the first common contact comprises:
 a first contact pattern in contact with the dummy pattern; and 
 a first gate contact electrically connected to the first gate electrode, 
 
 wherein the second common contact comprises:
 a second contact pattern in contact with the dummy pattern; and 
 a second gate contact electrically connected to the second gate electrode, and 
 
 wherein the first gate contact comprises:
 a first body part coupled to the first gate electrode; and 
 a first protrusion part that extends from the first body part and into the first contact pattern. 
 
 
     
     
       12. The semiconductor memory device of  claim 11 , wherein the second gate contact includes:
 a second body part coupled to the second gate electrode; and 
 a second protrusion part that extends from the second body part and into the second contact pattern. 
 
     
     
       13. The semiconductor memory device of  claim 11 , wherein a voltage applied to the first test line is different from a voltage applied to the second test line. 
     
     
       14. The semiconductor memory device of  claim 11 , further comprising:
 an active pattern on the memory cell region; 
 a source/drain pattern on the active pattern; 
 a third gate electrode on the active pattern and extending in the first direction, the third gate electrode being adjacent to the source/drain pattern in the second direction; and 
 a third common contact coupled to the source/drain pattern and the third gate electrode, the third common contact electrically connecting the source/drain pattern and the third gate electrode to each other, 
 wherein the third common contact comprises: 
 an active contact electrically connected to the source/drain pattern; and 
 a third gate contact electrically connected to the third gate electrode. 
 
     
     
       15. The semiconductor memory device of  claim 14 , wherein a lowermost level of a top surface of the active pattern is lower than a lowermost level of a top surface of the dummy pattern. 
     
     
       16. A semiconductor memory device, comprising:
 a substrate that includes a memory cell region and a test region; 
 an active pattern on the memory cell region; 
 a source/drain pattern on the active pattern; 
 a dummy pattern on the test region; 
 a device isolation layer on the substrate, a lower sidewall of each of the active pattern and the dummy pattern, wherein an upper portion of each of the active pattern and the dummy pattern protrudes upwardly from the device isolation layer; 
 a first gate electrode on the active pattern and extending in a first direction, wherein the first gate electrode and the source/drain pattern are adjacent to each other in a second direction that intersects the first direction; 
 a first common contact coupled to the source/drain pattern and the first gate electrode, wherein the first common contact electrically connects the source/drain pattern and the first gate electrode to each other; 
 a second gate electrode that extends in the first direction on the dummy pattern; 
 a second common contact in contact with the dummy pattern and the second gate electrode; 
 a gate spacer on a sidewall of each of the first and second gate electrodes; 
 a gate capping pattern on a top surface of each of the first and second gate electrodes; 
 an interlayer dielectric layer on the gate capping pattern; and 
 a first wiring layer, a second wiring layer, and a third wiring layer that are sequentially stacked on the interlayer dielectric layer, 
 wherein the first common contact comprises:
 an active contact that penetrates the interlayer dielectric layer and electrically connects with the source/drain pattern; and 
 a first gate contact that penetrates the gate capping pattern and electrically connects with the first gate electrode, 
 
 wherein the second common contact comprises:
 a first contact pattern that penetrates the interlayer dielectric layer and contacts the dummy pattern; and 
 
 a second gate contact that penetrates the gate capping pattern and electrically connects with the second gate electrode, 
 wherein the first gate contact comprises:
 a first body part coupled to the first gate electrode; and 
 a first protrusion part that extends from the first body part and into the active pattern, 
 
 wherein the second gate contact comprises:
 a second body part coupled to the second gate electrode; and 
 a second protrusion part that extends from the second body part and into the first contact pattern, 
 
 wherein the first wiring layer includes a first test line electrically connected to the second common contact, the first test line extending in the second direction, and 
 wherein a lowermost level of a top surface of the active pattern is lower than a lowermost level of a top surface of the dummy pattern. 
 
     
     
       17. The semiconductor memory device of  claim 16 , further comprising:
 a third gate electrode spaced apart in the second direction from the second gate electrode; and 
 a third common contact spaced apart in the first direction from the second common contact, 
 wherein the third common contact comprises:
 a second contact pattern that contacts the dummy pattern and extends in the first direction; and 
 a third gate contact electrically connected to the third gate electrode, and 
 
 wherein the first wiring layer further comprises a second test line electrically connected to the third common contact, the second test line extending in the second direction. 
 
     
     
       18. The semiconductor memory device of  claim 16 , wherein:
 a top surface of the device isolation layer on the memory cell region comprises a recess region that is recessed downwardly; and 
 a top surface of the device isolation layer on the test region is flat. 
 
     
     
       19. The semiconductor memory device of  claim 16 , further comprising a channel pattern connected to the source/drain pattern,
 wherein the first gate electrode covers a top surface, a bottom surface, and a sidewall of the channel pattern. 
 
     
     
       20. The semiconductor memory device of  claim 16 , wherein:
 the first wiring layer includes a bit line on the memory cell region; and 
 the third wiring layer includes a word line on the memory cell region.