Divided quad clock-based inter-die clocking in a three-dimensional stacked memory device

Abstract

A memory device includes a clock input configured to receive a clock from a host device. The memory device also includes a command input configured to receive command and address bits from the host device. The memory device further includes multiple die stacked in a three-dimensional stack. A first die of the plurality of die includes a first plurality of memory cells and first local control circuitry. The first local circuitry includes division circuitry configured to receive the clock from the clock input, generate a divided clock having a lower frequency than that of the clock, and generate multiple clocks from the divided clock with each of the multiple clocks having a lower frequency than the divided clock. The memory device also includes one or more transmitters configured to transmit the multiple clocks using a inter-die interconnects between the multiple die.

What is claimed is: 
     
       1. A memory device, comprising:
 a clock input configured to receive a clock from a host device; 
 a command input configured to receive command and address bits from the host device; and 
 a plurality of die stacked in a three-dimensional stack, wherein a first die of the plurality of die comprises:
 a first plurality of memory cells; and 
 first local control circuitry comprising:
 division circuitry configured to:
 receive the clock from the clock input; 
 generate a divided clock having a lower frequency than that of the clock; and 
 generate a plurality of component clocks from the divided clock with each of the plurality of component clocks having a lower frequency than the divided clock; and 
 
 one or more transmitters configured to transmit the plurality of component clocks using a plurality of inter-die interconnects between the plurality of die. 
 
 
 
     
     
       2. The memory device of  claim 1 , wherein the first die is a primary memory die, and the remaining die of the plurality of die are internal memory die that receive the plurality of component clocks from the primary memory die. 
     
     
       3. The memory device of  claim 2 , wherein the remaining die of the plurality of die each comprise:
 a second plurality of memory cells; 
 second local control circuitry comprising one or more receivers configured to receive the plurality of component clocks; and 
 clock reconstruction circuitry configured to reconstruct the divided clock from the plurality of component clocks. 
 
     
     
       4. The memory device of  claim 3 , wherein the clock reconstruction circuitry comprises a plurality of pulse generators each configured to generate a respective pulse signal based at least in part on a respective component clock of the plurality of component clocks. 
     
     
       5. The memory device of  claim 4 , wherein generating the respective pulse signal is based on only a rising edge of the corresponding component clock. 
     
     
       6. The memory device of  claim 4 , wherein the clock reconstruction circuitry comprises:
 a first logic gate to combine a first set of respective pulses corresponding to a first set of component clocks of the plurality of component clocks, wherein an output of the first logic gate is configured to cause a rising edge in the reconstructed divided clock; and 
 a second logic gate to combine a second set of respective pulses corresponding to a second set of component clocks of the plurality of component clocks, wherein an output of the second logic gate is configured to cause a falling edge in the reconstructed divided clock. 
 
     
     
       7. The memory device of  claim 6 , wherein the first logic gate comprises a first NOR gate, and the second logic gate comprises a second NOR gate. 
     
     
       8. The memory device of  claim 6 , wherein the clock reconstruction circuitry comprises a set-reset (SR) latch that is configured to:
 receive an output of the first logic gate at a first leg of the SR latch; 
 receive an output of the second logic gate at a second leg of the SR latch; and 
 output the reconstructed divided clock. 
 
     
     
       9. The memory device of  claim 8 , wherein the clock reconstruction circuitry comprises a pass gate at the second leg of the SR latch to balance propagation from the output of the first logic gate to the output of the SR latch with propagation from the output of the second logic gate to the output of the SR latch. 
     
     
       10. The memory device of  claim 1 , wherein the first local control circuitry comprises a primary memory die clock reconstruction circuitry that is inactive during operation of the memory device. 
     
     
       11. A memory device, comprising:
 a clock input configured to receive a clock from a host device; 
 a command input configured to receive command and address bits from the host device; 
 a first die comprising a first plurality of memory cells and first local control circuitry, wherein the first local control circuitry is configured to:
 receive the clock from the clock input; 
 receive the command and address bits from the command input; 
 transmit the command and address bits to a second die, wherein the first die and second die are arranged in a three-dimensional stack; 
 generate, in division circuitry of the first die, a divided clock from the clock in division circuitry; 
 generate, in the division circuitry, multiple clocks from the divided clock, wherein the multiple clocks have lower frequencies than the divided clock; and 
 transmit the multiple clocks to the second die; 
 
 a plurality of inter-die interconnects; and 
 the second die comprising:
 a second plurality of memory cells; and 
 second local control circuitry, wherein the second local control circuitry comprises:
 one or more receivers configured to receive the multiple clocks and the command and address bits from the first die via a first portion of the plurality of inter-die interconnects; 
 clock reconstruction circuitry configured to reconstruct, in the second die, the divided clock from the multiple clocks; and 
 a decoder configured to utilize the reconstructed divided clock to decode the command and address bits. 
 
 
 
     
     
       12. The memory device of  claim 11 , wherein the division circuitry comprises a first flip-flop configured to receive the clock and to generate the divided clock having half the frequency of the clock. 
     
     
       13. The memory device of  claim 12 , wherein the division circuitry comprises a second flip-flop configured to receive the divided clock and to generate a first clock of the multiple clocks having half the frequency of the divided clock. 
     
     
       14. The memory device of  claim 13 , wherein the division circuitry comprises a plurality of serially connected flip-flops that is configured to receive the first clock and shift out successive clocks of the multiple clocks. 
     
     
       15. The memory device of  claim 14 , wherein the shift between the successive clocks of the multiple clocks comprises a shift of one cycle of the clock. 
     
     
       16. The memory device of  claim 11 , wherein the first die comprises a bottom die of the three-dimensional stack. 
     
     
       17. The memory device of  claim 11 , wherein the plurality of inter-die interconnects between the first die and the second die comprises wirebonds, through-silicon vias, or a combination thereof. 
     
     
       18. The memory device of  claim 11 , comprising a third die in the three-dimensional stack, wherein the third die comprises:
 a third plurality of memory cells; and 
 third local control circuitry, wherein the third local control circuitry comprises:
 one or more additional receivers configured to receive the multiple clocks and the command and address bits from the first die via a second portion of the plurality of inter-die interconnects; 
 additional clock reconstruction circuitry configured to reconstruct, in the third die, an additional reconstructed divided clock from the multiple clocks; and 
 an additional decoder configured to utilize the reconstructed additional divided clock to decode the command and address bits. 
 
 
     
     
       19. A method, comprising:
 at a primary memory die of a three-dimensional stack of a memory device, receiving a clock from a host device; 
 in the primary memory die, dividing the clock to generate a divided clock; 
 in the primary memory die, dividing the divided clock to generate a plurality of lower frequency clocks having a frequency lower than a frequency of the divided clock; 
 transmitting the plurality of lower frequency clocks from the primary memory die to one or more internal memory die in the three-dimensional stack of the memory device using first inter-die interconnects; 
 at one or more internal memory die of the three-dimensional stack, receiving the plurality of lower frequency clocks from the primary memory die over the first inter-die interconnects; 
 in the one or more internal memory die, reconstructing the divided clock from the received lower frequency clocks; and 
 in the one or more internal memory die, decoding command and address bits using the reconstructed divided clock. 
 
     
     
       20. The method of  claim 19 , comprising:
 at the primary memory die of the three-dimensional stack, receiving the command and address bits from the host device; and 
 transmitting the command and address bits from the primary memory die to the one or more internal memory die via second inter-die interconnects. 
 
     
     
       21. The method of  claim 19 , wherein the first inter-die interconnects comprise wirebonds, through-silicon vias, or a combination thereof. 
     
     
       22. The method of  claim 19 , wherein transmitting the lower frequency clocks comprises transmitting the lower frequency clocks using one or more transmitters of the primary memory die, and receiving the lower frequency clocks comprises receiving the lower frequency clocks using one or more receivers of the one or more internal memory die.