Electronic device and method for fabricating the same

Abstract

An electronic device includes a semiconductor memory. A method for fabricating the electronic device includes forming a first memory cell extending vertically from a surface of substrate and having a first upper portion that protrudes laterally, forming a second memory cell extending vertically from the surface of the substrate and having a second upper portion that protrudes laterally towards the first upper portion, and forming a liner layer over the first and second memory cells, the liner layer having a first portion disposed over the first upper portion and a second portion disposed over the second upper portion, the first and second portions of the liner layer contacting each other.

What is claimed is: 
     
       1. A method for fabricating an electronic device including a semiconductor memory, the method comprising:
 forming first to fourth memory cells arranged in a matrix form along a first direction and a second direction crossing the first direction, each memory cell having a pillar structure that extends vertically from a surface of a substrate and includes a lower portion and an upper portion over the lower portion, the upper portion having a protruding portion that protrudes laterally beyond a sidewall of the lower portion; 
 forming a liner layer along the surface of the substrate and an entire side surface of each of the first to fourth memory cells without fully filling spaces between the lower portions of the first to fourth memory cells,
 wherein the liner layer has a first liner portion disposed over a first protruding portion of the first memory cell, a second liner portion disposed over a second protruding portion of the second memory cell, a third liner portion disposed over a third protruding portion of the third memory cell, and a fourth liner portion disposed over a fourth protruding portion of the fourth memory cell, 
 wherein among the first to fourth memory cells, two neighboring memory cells in the first direction or the second direction contact each other at a contact portion through corresponding liner portions among the first to fourth liner portions so as to provide spaces located under and over the contact portion, and 
 wherein an opening space is defined by the first to fourth liner portions in a plan view and surrounded by the first to fourth liner portions; and 
 
 providing an insulating material through the opening space so that the insulating material fills the spaces located under and over the contact portion and the opening space, the insulating material having a lower thermal conductivity than the liner layer. 
 
     
     
       2. The method according to  claim 1 , wherein the insulating material includes a flowable insulating material that includes SiOC, and
 wherein the lower portion of each memory cell includes a variable resistance pattern. 
 
     
     
       3. The method according to  claim 1 , wherein the upper portion of each memory cell includes an upper electrode, and
 wherein the upper electrode is formed to have a width increasing from top to bottom so that a side surface of the upper electrode forms an acute angle with the surface of the substrate. 
 
     
     
       4. The method according to  claim 3 , wherein the acute angle is in a range of 45° to 89°. 
     
     
       5. The method according to  claim 2 , wherein the variable resistance pattern includes a phase change material. 
     
     
       6. The method according to  claim 1 , wherein forming the liner layer comprises:
 forming a first liner layer along a profile of the first to fourth memory cells to encapsulate the first to fourth memory cells; and 
 forming a second liner layer over the first liner layer, 
 wherein forming the first liner layer and forming the second liner layer are performed along the profile of the first to fourth memory cells one or more times. 
 
     
     
       7. The method according to  claim 6 , wherein the first liner layer includes a nitride. 
     
     
       8. The method according to  claim 6 , wherein the second liner layer includes an oxide.