Memory device and operating method for target refresh operation based on number of accesses

Abstract

A semiconductor memory device includes: a memory cell region including normal cells and row-hammer cells coupled to each of a plurality of rows, wherein the row-hammer cells of a selected row are suitable for storing first data and second data, the first data representing a number of accesses to the selected row and the second data denoting whether to refresh second adjacent rows of the selected row; and a refresh control circuit suitable for: selecting a sampling address based on the first data read from a row corresponding to an input address when an active command is inputted, determining, in response to a refresh command, whether to refresh first adjacent rows of a target row corresponding to the sampling address, and determining, in response to the refresh command, whether to refresh second adjacent rows of the target row based on the second data read from the target row.

What is claimed is: 
     
       1. A semiconductor memory device, comprising:
 a memory cell region including a plurality of normal cells and a plurality of row-hammer cells coupled to each of a plurality of rows, wherein the row-hammer cells of a selected row are suitable for storing first data and second data, the first data representing a number of accesses to the selected row and the second data denoting whether to refresh second adjacent rows of the selected row; and 
 a refresh control circuit suitable for: 
 when an active command associated with an input address is inputted and based on the number of accesses read from the first data of the row-hammer cells corresponding to the input address, selecting a sampling address corresponding to the input address, 
 determining, in response to a refresh command, whether to refresh first adjacent rows physically closest to a target row corresponding to the sampling address, and 
 determining, in response to the refresh command, whether to refresh second adjacent rows physically adjacent to the target row, other than the first adjacent rows, based on the second data read from the target row. 
 
     
     
       2. The semiconductor memory device of  claim 1 ,
 wherein the rows are sequentially arranged in a column direction, and 
 wherein the first adjacent rows of an n-th row are (n±1)-th rows physically closest to the n-th row, and the second adjacent rows of the n-th row are (n±k)-th rows physically adjacent to the n-th row, where k is an integer greater than or equal to 2. 
 
     
     
       3. The semiconductor memory device of  claim 1 , wherein the refresh control circuit is further suitable for updating the first data and the second data stored in the row-hammer cells of the row corresponding to the input address when the active command is inputted. 
     
     
       4. The semiconductor memory device of  claim 1 , wherein the refresh control circuit is further suitable for issuing a target refresh command, when a number of inputs of the refresh command reaches a preset number, to refresh the first adjacent rows of the target row and to selectively refresh the second adjacent rows of the target row based on the second data, when the refresh command is inputted. 
     
     
       5. The semiconductor memory device of  claim 1 , wherein the refresh control circuit is further suitable for initializing, after the selective refresh of the second adjacent rows of the target row, the row-hammer cells of the target row. 
     
     
       6. The semiconductor memory device of  claim 1 , wherein the refresh control circuit includes:
 a command generation circuit suitable for generating a target refresh command according to the refresh command, and generating an internal read signal and an internal write signal according to the active command and a row-hammer reset signal; 
 a latch circuit suitable for storing, according to a latch enable signal, the input address and the first data respectively as the sampling address and maximum counting data; 
 a latch control circuit suitable for generating the latch enable signal by comparing the first data with the maximum counting data; and 
 a row-hammer analysis circuit suitable for calculating a plurality of adjacent addresses based on the sampling address, outputting a row-hammer address by scheduling the adjacent addresses based on the second data according to the target refresh command, and enabling the row-hammer reset signal. 
 
     
     
       7. The semiconductor memory device of  claim 6 , further comprising:
 a row control circuit suitable for refreshing one or more rows corresponding to the row-hammer address according to the target refresh command; and 
 a column control circuit suitable for outputting data from the row-hammer cells according to the internal read signal and writing data into the row-hammer cells according to the internal write signal. 
 
     
     
       8. The semiconductor memory device of  claim 6 , wherein the refresh control circuit further includes:
 a counting adjust circuit initialized by the row-hammer reset signal, and suitable for increasing the number represented by the first data according to the internal read signal; and 
 a comparison circuit initialized by the row-hammer reset signal, and suitable for updating the second data depending on whether the number becomes greater than or equal to a threshold value. 
 
     
     
       9. The semiconductor memory device of  claim 6 , wherein the row-hammer analysis circuit includes:
 an adjacent address calculating circuit suitable for calculating the adjacent addresses based on the sampling address; and 
 a row-hammer address output circuit suitable for scheduling the adjacent addresses based on the second data, outputting the scheduled adjacent addresses as the row-hammer address according to the target refresh command, and then enabling the row-hammer reset signal. 
 
     
     
       10. An operating method of a memory device including plural rows each comprising memory cells, the operating method comprising:
 updating, whenever accessing a selected row among the plural rows, first data representing an accumulated number of accesses to the selected row, the first data being stored in the selected row, the first data representing a number of accesses to the selected row; 
 updating second data when the accumulated number reaches a threshold, the second data being stored in the selected row, the second data denoting whether to refresh second rows of the plural rows; 
 refreshing first rows physically closest to a target row, which is identified on the basis of the first data stored in a row indicated by an active address among the plural rows; 
 refreshing, depending on the second data stored in the target row at a time of the refreshing of the first rows, the second rows physically adjacent to the target row than remaining rows other than the first rows among the plural rows; and 
 initializing the first data and the second data stored in the target row after the refreshing of the second rows.