Memory system

Abstract

According to one embodiment, a memory system includes: a plurality of memory chips; a plurality of memory controllers; and a data encoding circuit configured to form a first group including a continuous plurality of first divided data among the user data, and generate a plurality of first page data. The memory controllers adjust a schedule of a write operation among the memory controllers and control a number of the write operations to be simultaneously executed. When at least one of the memory chips is in a busy state in a first read request, the memory controller connected to the memory chip in the busy state decodes the first divided data through erasure correction decoding processing using the first divided data read from the memory chip not in the busy state.

The invention claimed is: 
     
       1. A memory system comprising:
 a plurality of memory chips respectively including a plurality of first memory cells in which first page data is collectively written and a plurality of second memory cells in which second page data is collectively written; 
 a plurality of memory controllers respectively connected to the memory chips; and 
 a data encoding circuit configured to:
 divide user data into a plurality of first divided data or a plurality of second divided data, the plurality of first divided data respectively having a first data size smaller than a page size for collectively writing data into one of the memory chips, two or more of the first data sizes being included in the page size, the plurality of second divided data respectively having a second data size corresponding to the page size and larger than the first data size; 
 form a first group including a plurality of third divided data, the plurality of third divided data being included in the plurality of first divided data and having continuous logical addresses; 
 generate a plurality of first page data in which the plurality of third divided data are distributed on the memory chips; and 
 
 generate a plurality of second page data in which the plurality of second divided data are distributed on the memory chips; 
 wherein 
 the memory controllers are configured to adjust a schedule of a write operation among the memory controllers, control a number of the write operations to be simultaneously executed, and write the plurality of first page data in the memory chips, and 
 when at least one of the memory chips is in a busy state in a first read request for the plurality of third divided data, the memory controller connected to the memory chip in the busy state is configured to decode the third divided data stored in the memory chip in the busy state through erasure correction decoding processing using the third divided data read from the memory chip not in the busy state. 
 
     
     
       2. The memory system according to  claim 1 , wherein
 the first read request for the plurality of third divided data is prioritized over a second read request for plurality of the second divided data. 
 
     
     
       3. The memory system according to  claim 2 , wherein
 the second read request for the plurality of second divided data is prioritized over a write request. 
 
     
     
       4. The memory system according to  claim 2 , wherein
 in the first read request for the plurality of third divided data, a memory chip not executing a read operation of the plurality of third divided data executes the read operation of the plurality of second divided data or the write operation. 
 
     
     
       5. The memory system according to  claim 2 , wherein
 when a number of write requests is larger than a preset number; the write request is prioritized over the first read request for the plurality of third divided data, and 
 the memory controllers are configured to execute the write operations without adjusting the schedule of the write operations among the memory controllers. 
 
     
     
       6. The memory system according to  claim 1 , wherein
 an error correction code added to each of the plurality of third divided data and an error correction code added to each of the plurality of second divided data have different schemes. 
 
     
     
       7. The memory system according to  claim 1 , wherein
 an error correction code added to each of the plurality of third divided data and an error correction code added to each of the plurality of second divided data have a same scheme. 
 
     
     
       8. The memory system according to  claim 1 , wherein
 the data encoding circuit is configured to generate a plurality of third page data, each of the plurality of third page data including a plurality of fourth divided data included in the plurality of first divided data and having continuous logical addresses, and 
 each of the memory chips stores one of the plurality of first page data and one of the plurality of third page data. 
 
     
     
       9. The memory system according to  claim 1 , wherein
 the data encoding circuit is configured to form a second group including a plurality of fifth divided data included in the plurality of first divided data and having, continuous logical addresses, and 
 one of the plurality of first page data includes one of the plurality of third divided data and one of the plurality of plurality fifth divided data, and a logical address of the one of the plurality of third divided data and a logical address of the one of the plurality of fifth divided data are not continuous. 
 
     
     
       10. The memory system according to  claim 1 , wherein
 the memory chips respectively include a plurality of second memory cells in which data is collectively written, 
 the first memory cells correspond to the plurality of first page data and the second memory cells correspond to the plurality of second page data, and 
 each of the first memory cells is capable of holding one-bit or larger data and each of the second memory cells is capable of holding data with a larger number of bits than each of the first memory cells. 
 
     
     
       11. The memory system according to  claim 1 , wherein
 the first memory cells are capable of storing one of the plurality of first page data and one of the plurality of second page data, and 
 a number of read levels for determining the one of the plurality of first page data is smaller than a number of read levels for determining the one of plurality of the second page data. 
 
     
     
       12. The memory system according to  claim 1 , wherein
 in the first read request for the plurality of third divided data, in a case where the memory chip in the busy state is executing the write operation and a period until a scheduled end of the write operation is longer than a preset period, the memory controller connected to the memory chip in the busy state suspends the write operation and executes a read operation of the plurality of third divided data. 
 
     
     
       13. The memory system according to  claim 1 , wherein
 in the first read request tor the plurality of third divided data, in a case where the memory chip in the busy state is executing the write operation and a period until a scheduled end of the write operation is equal to or shorter than a preset period, the memory controller connected to the memory chip in the busy state stays on standby until the memory chip in the busy state comes into a ready state and executes a read operation of the third divided data. 
 
     
     
       14. The memory system according to  claim 1 , wherein
 a read operation includes a first read operation and a second read operation having longer latency than the first read operation, 
 in the first read request for the plurality of third divided data, each of the controllers selects the first read operation in a case where an exhaustion degree of the first memory cells corresponding thereto is equal to or smaller than a preset first threshold and selects the second read operation in a case where the exhaustion degree is larger than the first threshold, and 
 in a second read request for the plurality of second divided data, each of the controllers selects the first read operation when the exhaustion degree of the corresponding plurality of first memory cells is equal to or smaller than a preset second threshold and selects the second read operation when the exhaustion degree is larger than the second threshold. 
 
     
     
       15. The memory system according to  claim 1 , wherein each of the memory controllers includes a determination circuit configured to acquire congestion degree information of the memory chips and determine a congestion degree of a memory chip corresponding thereto. 
     
     
       16. The memory system according to  claim 1 , wherein a number of divided data capable of encoding by the erasure correction decoding processing and a number of the write operations to be simultaneously executed are same. 
     
     
       17. The memory system according to  claim 1 , wherein
 the first group further includes an erasure correction code based on the plurality of third divided data, 
 the erasure correction code is stored in a first memory chip that is one of the memory chips and the plurality of third divided data are stored in at least one of the memory chips other than the first memory chip, and 
 when at least one of the memory chips storing the plurality of third divided data is in a busy state in the first read request for the plurality of third divided data, the memory controller connected to the memory chip in the busy state is configured to decode the third divided data stored in the memory chip in the busy state through erasure correction decoding processing using the third divided data and the erasure correction code read from the memory chips not in the busy state. 
 
     
     
       18. The memory system according to  claim 1 , wherein
 a third data size read from one of the memory chips corresponding to the first read request for the plurality of the third divided data is different from a fourth data size read from one of the memory chips corresponding to a second read request for the plurality of the second divided data. 
 
     
     
       19. The memory system according to  claim 18 , wherein
 the third data size is smaller than the fourth data size.