Data relocation in memory

Abstract

The present disclosure includes apparatuses, methods, and systems for data relocation in memory. An embodiment includes a controller, and a memory having a plurality of physical units of memory cells. Each of the physical units has a different sequential physical address associated therewith, a first number of the physical units have data stored therein, a second number of the physical units do not have data stored therein, and the physical address associated with each respective one of the second number of physical units is a different consecutive physical address in the sequence. The controller can relocate the data stored in the physical unit of the first number of physical units, whose physical address in the sequence is immediately before the first of the consecutive physical addresses associated with the second number of physical units, to the last of the consecutive physical addresses associated with the second number of physical units.

What is claimed is: 
     
       1. An apparatus, comprising:
 a memory having a plurality of physical blocks of memory cells, wherein:
 a first plurality of the physical blocks have data stored therein; 
 a second plurality of the physical blocks do not have data stored therein; and 
 each of the physical blocks has a different sequential physical address associated therewith; and 
 
 circuitry configured to relocate data stored in a physical block of the first plurality of physical blocks, whose physical address in the sequence is immediately before a first of the sequential physical addresses associated with the second plurality of physical blocks, to a last of the sequential physical addresses associated with the second plurality of physical blocks, wherein the last of the sequential physical addresses is associated with a different one of the second plurality of physical blocks than the first of the sequential physical addresses. 
 
     
     
       2. The apparatus of  claim 1 , wherein the plurality of physical blocks of memory cells comprise a group of memory cells. 
     
     
       3. The apparatus of  claim 2 , wherein:
 the memory includes a number of additional groups of memory cells, wherein:
 each respective additional group includes a plurality of physical blocks of memory cells; 
 a first number of the physical blocks of each respective additional group have data stored therein; 
 a second number of the physical blocks of each respective additional group do not have data stored therein; and 
 each of the physical blocks of each respective additional group has a different physical address associated therewith; and 
 
 the circuitry is configured to, for each respective additional group, relocate data stored in a physical block of the first number of physical blocks of that respective additional group to a physical address of the physical addresses associated with the second number of physical blocks of that respective additional group. 
 
     
     
       4. The apparatus of  claim 1 , wherein the circuitry is configured to randomize logical addresses associated with the first plurality of physical blocks after the data has been relocated from the physical block of the first plurality of physical blocks. 
     
     
       5. The apparatus of  claim 1 , wherein the circuitry is configured to initiate the relocation of the data from the physical block of the first plurality of physical blocks in response to a particular number of program operations being performed on the memory. 
     
     
       6. A method of operating memory, comprising:
 relocating data stored in a first physical block of the memory to a second physical block of the memory, wherein:
 the first physical block of the memory is one of a plurality of physical blocks of the memory that have data stored therein; 
 the second physical block of the memory is one of a plurality of physical blocks of the memory that do not have data stored therein and have different sequential physical addresses associated therewith; 
 the physical address associated with the second physical block of the memory is the last of the physical addresses in the sequence; 
 the first physical block of the memory has a physical address associated therewith that is immediately before the first of the physical addresses in the sequence; and 
 the last of the physical addresses in the sequence is associated with a different one of the plurality of physical blocks of memory that do not have data stored therein than the first of the physical addresses in the sequence. 
 
 
     
     
       7. The method of  claim 6 , wherein the method includes changing a quantity of the plurality of physical blocks of the memory that do not have data stored therein. 
     
     
       8. The method of  claim 7 , wherein the method includes relocating the data stored in the first physical block of the memory to the second physical block of the memory after changing the quantity of the plurality of physical blocks of the memory that do not have data stored therein. 
     
     
       9. The method of  claim 6 , wherein the method includes identifying the second physical block of the memory to which the data stored in the first physical block of the memory has been relocated using algebraic mapping. 
     
     
       10. The method of  claim 6 , wherein relocating the data stored in the first physical block of the memory to the second physical block of the memory results in:
 the first physical block of the memory becoming one of the plurality of physical blocks of the memory that do not have data stored therein and have different sequential physical addresses associated therewith; and 
 the second physical block of the memory becoming one of the plurality of physical blocks of the memory that have data stored therein. 
 
     
     
       11. An apparatus, comprising:
 a memory having a plurality of physical blocks of memory cells, wherein:
 each of the physical blocks has a different sequential address associated therewith; 
 a first plurality of the physical blocks have data stored therein; and 
 a second plurality of the physical blocks do not have data stored therein, wherein the address associated with each respective one of the second plurality of physical blocks is a different consecutive address in the sequence; and 
 
 circuitry configured to relocate the data stored in the physical block of the first plurality of physical blocks, whose address in the sequence is immediately before the first of the consecutive addresses associated with the second plurality of physical blocks, to the last of the consecutive addresses associated with the second plurality of physical blocks, wherein the last of the consecutive addresses is associated with a different one of the second plurality of physical blocks than the first of the consecutive addresses. 
 
     
     
       12. The apparatus of  claim 11 , wherein the addresses in the sequence comprise physical addresses. 
     
     
       13. The apparatus of  claim 11 , wherein the second plurality of physical blocks that do not have data stored therein comprises a prime number of physical blocks. 
     
     
       14. The apparatus of  claim 11 , wherein the circuitry is configured to relocate the data stored in the physical block of the first plurality of physical blocks to the last of the consecutive addresses associated with the second plurality of physical blocks without using a table. 
     
     
       15. The apparatus of  claim 11 , wherein the circuitry is configured to relocate the data stored in the physical block of the first plurality of physical blocks to the last of the consecutive addresses associated with the second plurality of physical blocks using algebraic mapping. 
     
     
       16. The apparatus of  claim 11 , wherein the circuitry comprises hardware.