Chamfer-less via integration scheme

Abstract

Methods and apparatuses for processing semiconductor substrates in an integration scheme to form chamferless vias are provided herein. Methods include bifurcating etching of dielectric by depositing a conformal removable sealant layer having properties for selective removal relative to dielectric material without damaging dielectric material. Some methods include forming an ashable conformal sealant layer. Methods also include forming hard masks including a Group IV metal and removing conformal removable sealant layers and hard masks in one operation using same etching chemistries.

What is claimed is: 
     
       1. A method comprising:
 providing a substrate having a trench formed in a dielectric material; 
 depositing a selectively removable sealant layer conformally in the trench, 
 wherein the selectively removable sealant layer comprises a Group IV metal; 
 forming a patterned hard mask on the selectively removable sealant layer; 
 etching the dielectric material using the patterned hard mask; and 
 removing the patterned hard mask and the selectively removable sealant layer to produce a chamferless via. 
 
     
     
       2. The method of  claim 1 , wherein the Group IV metal is selected from the group consisting of tin and lead. 
     
     
       3. The method of  claim 1 , wherein the selectively removable sealant layer is selected from the group consisting of tin oxide, tin nitride, tin sulfide, lead oxide, lead nitride, lead sulfide, and combinations thereof; and wherein the selectively removable sealant layer comprises one or more than one layer. 
     
     
       4. The method of  claim 1 , further comprising:
 selectively removing the selectively removable sealant layer relative to the dielectric material using hydrogen gas or an organic acid. 
 
     
     
       5. The method of  claim 1 , wherein the trench comprises an opening and a bottom, and a distance from the opening to the bottom is at least about 25% of a total thickness of the dielectric material. 
     
     
       6. The method of  claim 1 , wherein the substrate further comprises a metal hard mask over the dielectric material. 
     
     
       7. The method of  claim 1 , wherein the patterned hard mask is removable using a hydrogen-containing gas. 
     
     
       8. The method of  claim 1 , wherein the dielectric material is an ultra-low-k silicon oxide. 
     
     
       9. The method of  claim 4 , wherein the organic acid is selected from the group consisting of acetic acid and citric acid. 
     
     
       10. The method of  claim 6 , further comprising:
 selectively removing the metal hard mask relative to the dielectric material using a hydrogen-containing gas. 
 
     
     
       11. The method of  claim 10 , wherein the hydrogen-containing gas is selected from the group consisting of hydrogen (H 2 ), methane (CH 4 ), ethylene (C 2 H 4 ), ammonia (NH 3 ), and mixtures thereof. 
     
     
       12. The method of  claim 1 , wherein the selectively removable sealant layer comprises two layers, and wherein the two layer optionally have different composition. 
     
     
       13. The method of  claim 7 , wherein the patterned hard mask comprises spin-on carbon. 
     
     
       14. A method, the method comprising:
 providing a semiconductor substrate comprising a layer of material, a removable sealant layer on the layer of material, and a patterned hard mask directly on the removable sealant layer, the layer of material comprising dielectric material and a metal underlying the dielectric material; 
 selectively etching the removable sealant layer relative to the dielectric material to expose the dielectric material; 
 etching the dielectric material using the patterned hard mask to expose a surface of the metal; and 
 removing the patterned hard mask and the removable sealant layer completely to form a via exposing the surface of the metal. 
 
     
     
       15. The method of  claim 14 , wherein the etching the dielectric material comprises exposing the dielectric material to an oxygen-containing reactant. 
     
     
       16. The method of  claim 14 , wherein the selectively etching the removable sealant layer comprises applying a bias. 
     
     
       17. A method comprising:
 providing a semiconductor substrate having a dielectric material comprising (i) a trench and a first patterned hard mask or (ii) a trench formed by a first patterned hard mask; 
 depositing a removable sealant layer conformally over the dielectric material, wherein the removable sealant layer comprises a Group IV metal; 
 forming a second patterned mask over the removable sealant layer; 
 etching the dielectric material using the second patterned mask; 
 selectively removing the second patterned mask relative to the removable sealant layer and dielectric material; and 
 selectively removing the removable sealant layer relative to the dielectric material. 
 
     
     
       18. The method of  claim 17 , wherein the selectively removing the second patterned mask and the selectively removing the removable sealant layer are performed using the same etching chemistry. 
     
     
       19. The method of  claim 18 , wherein the etching chemistry comprises a hydrogen-containing gas. 
     
     
       20. The method of  claim 17 , further comprising selectively removing the first patterned hard mask relative to other exposed surfaces on the semiconductor substrate. 
     
     
       21. The method of  claim 20 , wherein the selectively removing the removable sealant layer is performed using the same etching chemistry as the selectively removing the second patterned mask and/or selectively removing the first patterned hard mask. 
     
     
       22. The method of  claim 21 , wherein the etching chemistry comprises a hydrogen-containing gas. 
     
     
       23. A method comprising:
 providing a substrate having dielectric disposed over a metal surface; 
 etching the dielectric to form a via to the metal surface; and 
 bifurcating the etch of the dielectric by: 
 etching a first amount of the dielectric to form a trench, wherein the first amount of the dielectric etched is between about 50% and about 75% of a total thickness of the dielectric, 
 etching a second amount of the dielectric to expose the metal surface, and 
 depositing a removable sealant layer over the dielectric, patterning a hard mask over the removable sealant layer, between a time of the etching the first amount of the dielectric and a time of the etching the second amount of the dielectric. 
 
     
     
       24. The method of  claim 23 , wherein the removable sealant layer comprises tin nitride deposited using anaerobic conditions, a tin oxide, or an underlayer of tin nitride and a top layer of tin oxide; and wherein the removable sealant layer comprises one or more than one layer. 
     
     
       25. The method of  claim 17 , comprising, after the forming the second patterned mask:
 selectively etching the removable sealant layer by exposing the removable sealant layer to a hydrogen-containing gas and applying a bias; and 
 wherein the selectively removing the second patterned mask and the selectively removing the removable sealant layer uses a hydrogen-containing gas. 
 
     
     
       26. An apparatus comprising:
 (a) a process chamber comprising a pedestal for holding a substrate; 
 (b) at least one outlet for coupling to a vacuum; and 
 (c) a controller for controlling operations in the apparatus, comprising machine-readable instructions for:
 (i) causing introduction of a Group IV metal-containing precursor and a carbon-based layer over a layer formed using the Group IV metal-containing precursor over a dielectric material; 
 (ii) causing introduction of an oxygen-containing or nitrogen-containing reactant to selectively remove the dielectric material using the carbon-based layer; and 
 (iii) causing introduction of a hydrogen-containing gas to remove the carbon-based layer. 
 
 
     
     
       27. The apparatus of  claim 26 , wherein:
 the layer formed using the Group IV metal-containing precursor comprises a selectively removable sealant layer formed over the dielectric material; and 
 the carbon-based layer comprises a patterned hard mask.