Memory system for performing recovery operation, memory device, and method of operating the same

Abstract

A method of operating a memory system that comprises a memory device including a plurality of memory blocks and a memory controller, includes detecting a first memory block having a degradation count greater than or equal to a first reference value by the memory controller. A first command for the first memory block is transmitted to the memory device by the memory controller. A first voltage is applied to all of a plurality of word lines connected to the first memory block and a second voltage to a bit line connected to the first memory block in response to the first command by the memory device. The first voltage is greater than a voltage applied to turn on memory cells connected to all of the plurality of word lines. The second voltage is greater than a voltage applied to the bit line during program, read or erase operations.

What is claimed is: 
     
       1. A method of operating a memory system that comprises a memory device including a plurality of memory blocks and a memory controller, the method comprising:
 detecting a first memory block having a degradation count greater than or equal to a first reference value from among the plurality of memory blocks by the memory controller; 
 transmitting a first command for the first memory block to the memory device by the memory controller; and 
 performing a recovery operation by applying a first voltage to all of a plurality of word lines connected to the first memory block and a second voltage to a bit line connected to the first memory block in response to the first command by the memory device, wherein: 
 the first voltage is greater than a voltage applied to turn on memory cells connected to all of the plurality of word lines connected to the first memory block; and 
 the second voltage is greater than a voltage applied to the bit line during a program operation, a read operation, or an erase operation performed on the memory device. 
 
     
     
       2. The method of  claim 1 , wherein the recovery operation is performed during an idle time of the memory device. 
     
     
       3. The method of  claim 1 , wherein the degradation count is program-erase counts for the plurality of memory blocks or error bit counts obtained from the plurality of memory blocks. 
     
     
       4. The method of  claim 3 , wherein the detecting of the first memory block having the degradation count greater than or equal to the first reference value comprises:
 transmitting a second command for requesting data stored in the first memory block to the memory device by the memory controller; 
 transmitting the data to the memory controller by the memory device; and 
 counting error bits of the data by the memory controller. 
 
     
     
       5. The method of  claim 3 , further comprising:
 detecting a second memory block having a degradation count that is greater than or equal to a second reference value from among the plurality of memory blocks by the memory controller; and 
 setting the second memory block as a bad block by the memory controller, wherein the second reference value is greater than the first reference value. 
 
     
     
       6. The method of  claim 1 , further comprising:
 before performing the recovery operation, copying first data stored on the first memory block and storing the first data on a second memory block from among the plurality of memory blocks; and 
 erasing the first data stored on the first memory block. 
 
     
     
       7. The method of  claim 6 , further comprising:
 detecting a third memory block having the degradation count greater than or equal to the first reference value from among the plurality of memory blocks; 
 copying second data stored on the third memory block and storing the second data on a fourth memory block from among the plurality of memory blocks; 
 erasing the second data stored on the third memory block while the recovery operation is performed on the first memory block; and 
 performing a second recovery operation on the third memory block by applying the first voltage to all of a plurality of word lines connected to the third memory block and the second, voltage to a bit line connected to the third memory block by the memory device. 
 
     
     
       8. The method of  claim 1 , wherein:
 the plurality of memory blocks comprises a first memory stack and a second memory stack; and 
 the first memory stack and the second memory stack are formed through independent channel hole generation processes, respectively. 
 
     
     
       9. The method of  claim 6 , further comprising, after the first data is copied and stored on the second memory block, updating a physical address mapped with a logical address for the first data from a physical address of the first memory block to a physical address of the second memory block. 
     
     
       10. The method of  claim 1 , further comprising initializing the degradation count of the first memory block by the memory controller. 
     
     
       11. The method of  claim 10 , further comprising setting the first memory block as a bad block based on whether an initialization count of the degradation count is greater than or equal to a reference number. 
     
     
       12. A memory device comprising:
 a memory cell array comprising a plurality of memory blocks, each of the plurality of memory blocks comprising a plurality of memory cells, a plurality of word lines respectively connected to the plurality of memory blocks, and a plurality of bit lines respectively connected to the plurality of memory blocks; and 
 a control circuit controlling the memory device to perform a control operation on a first memory block from among the plurality of memory blocks, 
 wherein, during the control operation, the control circuit: 
 copies first data stored on the first memory block from among the plurality of memory blocks and stores the first data on a second memory block from among the plurality of memory blocks and erases the first data stored on the first memory block, 
 applies a first voltage to some selected word lines from among a plurality of word lines connected to the first memory block and applies a second voltage to a bit line connected to the first memory block among the plurality of bit lines, 
 controls the first voltage to be greater than a voltage applied to turn on memory cells connected to the some selected word lines from among the word lines connected to the first memory block, and 
 controls the second voltage to be greater than a voltage applied to the bit line during a program operation, a read operation, or an erase operation performed on the memory cell array. 
 
     
     
       13. The memory device of  claim 12 , wherein the memory cells of the memory device have a silicon-on-insulator structure. 
     
     
       14. The memory device of  claim 12 , wherein the each of the plurality of memory blocks comprises:
 a first memory stack comprising a plurality of first memory cells; and 
 a second memory stack comprising a plurality of second memory cells that is formed through a channel hole formation process independent from the first memory stack and vertically stacked on the first memory stack. 
 
     
     
       15. A memory system comprising:
 a memory device comprising a plurality of memory blocks; and 
 a memory controller transmitting commands to control the memory device, wherein: 
 in response to the commands, the memory device copies first data stored on a first memory block from among the plurality of memory blocks and stores the first data on a second memory block from among the plurality of memory blocks, erases the first data stored on the first memory block, applies a first voltage to all of word lines connected to the first memory block, and applies a second voltage to a bit line connected to the first memory block, wherein: 
 the first voltage is greater than a voltage applied to turn on memory cells connected to all of the word lines connected to the first memory block; and 
 the second voltage is greater than a voltage applied to the bit line during a pre-charging operation for the memory device. 
 
     
     
       16. The memory system of  claim 15 , wherein the memory controller selects a memory block having a degradation count greater than or equal to a reference value from among the plurality of memory blocks as the first memory block and provides an address of the first memory block to the memory device. 
     
     
       17. The memory system of  claim 16 , wherein the reference value differs from one memory block to another memory block of the plurality of memory blocks. 
     
     
       18. The memory system of  claim 15 , wherein each of the plurality of memory blocks comprises:
 a first memory stack comprising a plurality of first memory cells; and 
 a second memory stack comprising a plurality of second memory cells formed through a channel hole formation process independent from the first memory stack and vertically stacked on the first memory stack. 
 
     
     
       19. The memory system of  claim 16 , wherein the memory controller determines error bits of the first memory block after detecting the first memory block having a degradation count greater than or equal to the reference value. 
     
     
       20. The memory system of  claim 15 , wherein each of the plurality of memory blocks comprises:
 an upper substrate; 
 a plurality of gate conductive layers stacked on the upper substrate and respectively connected to word lines; and 
 a plurality of channel layers penetrating through the gate conductive layers and extending in a direction perpendicular to a top surface of the upper substrate.