Input signal correction device

Abstract

An input signal correction device for reducing power consumption is compatible with a variety of display panels, and includes an input circuit, extension/degeneration circuit, separation/recovery circuit and delay adjustment circuit operating at frequency f, demura circuit operating at frequency f/2, and adder circuit. The extension/degeneration circuit outputs a preprocessing signal increasing the input signal cycle length by 2 or outputs by degenerating the input signal to ½, based on a control signal, the demura circuit outputs a correction signal correcting the preprocessing signal from the extension/degeneration circuit, the separation/recovery circuit outputs a differential signal reducing the correction signal cycle length to ½ or reduces cycle length to ½ and outputs the same differential signal over two cycles, based on a control signal, the delay adjustment circuit outputs a delay signal delaying the input signal, and the adder circuit outputs a signal adding the differential signal to the delay signal.

The invention claimed is: 
     
       1. An input signal correction device for correcting input signals for a display panel in which numbers of R, G and B subpixels are equal or unequal at a ratio of minority subpixels to majority subpixels of 1:N, where N is an integer of 2 or more, comprising:
 an input circuit configured to operate at operating frequency f, and for each of the R, G and B subpixels, to receive input of an input signal; 
 an extension/degeneration circuit configured to operate at operating frequency f and to receive input of a first control signal and, for each of the R, G and B subpixels, output a preprocessing signal by increasing a cycle length of the input signal by a factor of N or output a preprocessing signal by degenerating the input signal to 1/N, based on the first control signal; 
 a correction circuit configured to operate at operating frequency f/N and, for each of the R, G and B subpixels, to output a correction signal by correcting the preprocessing signal; 
 a separation/recovery circuit configured to operate at operating frequency f and to receive input of a second control signal and, for each of the R, G and B subpixels, output a differential signal by reducing the cycle length of the correction signal to 1/N or reduce the cycle length of the correction signal to 1/N and output a same differential signal over N cycles, based on the second control signal; 
 a delay adjustment circuit configured to operate at operating frequency f, and for each of the R, G and B subpixels, to output a delay signal by delaying the input signal; and 
 an adder circuit configured to, for each of the R, G and B subpixels, add the differential signal to the delay signal. 
 
     
     
       2. The input signal correction device according to  claim 1 , comprising:
 a clock circuit configured to generate a clock signal of operating frequency f to be input to the input circuit, the extension/degeneration circuit, the separation/recovery circuit, and the delay adjustment circuit; and 
 a frequency divider circuit configured to generate a clock signal of operating frequency f/N to be input to the correction circuit, by dividing a frequency of the clock signal of operating frequency f. 
 
     
     
       3. The input signal correction device according to  claim 2 ,
 wherein the correction circuit outputs the correction signal by correcting the preprocessing signal to reduce mura defects of the display panel. 
 
     
     
       4. The input signal correction device according to  claim 1 ,
 wherein the correction circuit outputs the correction signal by correcting the preprocessing signal to reduce mura defects of the display panel. 
 
     
     
       5. An input signal correction device for correcting input signals for a display panel in which numbers of R, G and B subpixels are equal or unequal at a ratio of minority subpixels to majority subpixels of 1:N, where N is an integer of 2 or more, comprising:
 an input circuit configured to operate based on a clock signal of frequency f, and for each of the R, G and B subpixels, to receive input of an input signal; 
 an extension/degeneration circuit configured to operate based on the clock signal and to receive input of a first control signal and, for each of the R, G and B subpixels, output a preprocessing signal by increasing a cycle length of the input signal by a factor of N or output a preprocessing signal by degenerating the input signal to 1/N, based on the first control signal; 
 a correction circuit configured to operate based on the clock signal and to receive input of a clock enable signal for switching between enabling and disabling the clock signal at frequency f/N and, for each of the R, G and B subpixels, output a correction signal by correcting the preprocessing signal; 
 a separation/recovery circuit configured to operate based on the clock signal and to receive input of a second control signal and, for each of the R, G and B subpixels, output a differential signal by reducing the cycle length of the correction signal to 1/N or reduce the cycle length of the correction signal to 1/N and output a same differential signal over N cycles, based on the second control signal; 
 a delay adjustment circuit configured to operate based on the clock signal and, for each of the R, G and B subpixels, to output a delay signal by delaying the input signal; and 
 an adder circuit configured to, for each of the R, G and B subpixels, add the differential signal to the delay signal. 
 
     
     
       6. The input signal correction device according to  claim 5 , comprising:
 a clock circuit configured to generate the clock signal; and 
 a clock enable circuit configured to generate the clock enable signal based on the clock signal. 
 
     
     
       7. The input signal correction device according to  claim 6 ,
 wherein the correction circuit outputs the correction signal by correcting the preprocessing signal to reduce mura defects of the display panel. 
 
     
     
       8. The input signal correction device according to  claim 5 ,
 wherein the correction circuit outputs the correction signal by correcting the preprocessing signal to reduce mura defects of the display panel.