Hybrid parallel programming of single-level cell memory

Abstract

A memory device includes a page buffer with a cache register and data registers, a memory array with a set of sub-blocks of memory cells configured as single-level cell (SLC) memory, and control logic. The control logic performs operations including: causing a first page of SLC data to be stored in the cache register; causing the first page of the SLC data to be moved from the cache register to a first data register; causing a subsequent page of the SLC data to be stored in the cache register; causing the SLC data stored in the cache register and in the data registers to be concurrently programmed to the set of sub-blocks, where the first page is programmed to a first sub-block and the subsequent page is programmed to a subsequent sub-block; and causing a subset of the operations for programming the set of sub-blocks to be performed in parallel.

What is claimed is: 
     
       1. A memory device comprising:
 a page buffer comprising a cache register and multiple data registers; 
 a memory array comprising a set of sub-blocks coupled with the page buffer, wherein the set of sub-blocks comprises memory cells configured as single-level cell (SLC) memory; and 
 control logic operatively coupled with the page buffer, the control logic to perform operations comprising:
 causing a first page of SLC data to be stored in the cache register; 
 causing the first page of the SLC data to be moved from the cache register to a first data register of the multiple data registers; 
 causing a subsequent page of the SLC data to be stored in the cache register; 
 causing the subsequent page and the first page of the SLC data stored in the cache register and in the first data register, respectively, to be concurrently programmed to the set of sub-blocks, wherein the first page is programmed to a first sub-block and the subsequent page is programmed to a subsequent sub-block of the set of sub-blocks; and 
 causing the operations for programming the set of sub-blocks to be performed in parallel. 
 
 
     
     
       2. The memory device of  claim 1 , wherein the set of sub-blocks comprise four sub-blocks of SLC cache and the SLC data comprises four pages. 
     
     
       3. The memory device of  claim 2 , wherein the subsequent page is a fourth page of the four pages, and wherein the operations further comprise:
 causing a second page of the SLC data to be stored in the cache register; 
 causing the second page of the SLC data to be moved from the cache register to a second data register of the multiple data registers; 
 causing a third page of the SLC data to be stored in the cache register; and 
 causing the third page of the SLC data to be moved from the cache register to a third data register of the multiple data registers. 
 
     
     
       4. The memory device of  claim 3 , wherein causing the subsequent page and the first page of the SLC data to be concurrently programmed to the set of sub-blocks further comprises concurrently:
 causing the second page to be programmed to a second sub-block of the set of sub-blocks; 
 causing the third page to be programmed to a third sub-block of the set of sub-blocks; and 
 wherein the subsequent sub-block is a fourth sub-block of the set of sub-blocks. 
 
     
     
       5. The memory device of  claim 1 , wherein the set of sub-blocks comprise two sub-blocks of SLC cache, the subsequent page is a second page of two pages SLC data, and wherein causing the subsequent page and the first page of the SLC data to be concurrently programmed to the set of sub-blocks comprises cache programming. 
     
     
       6. The memory device of  claim 1 , wherein the operations further comprise:
 causing charge pump initialization to be performed for the set of sub-blocks; 
 causing a program verify initialization to be performed for the set of sub-blocks; and 
 causing bitlines and wordlines to be discharged during a voltage recovery phase. 
 
     
     
       7. The memory device of  claim 6 , wherein the operations for programming the set of sub-blocks further comprise selecting one or more bitlines not to be involved with programming. 
     
     
       8. The memory device of  claim 6 , wherein the operations further comprise:
 causing a selected bitline and a selected source voltage line to be charged to target voltages in preparation for programming a sub-block coupled between the selected bitline and the selected source voltage line; and 
 causing voltages to a select gate line and a select source line to ramp to predetermined voltages, respectively. 
 
     
     
       9. The memory device of  claim 6 , wherein the operations further comprise serially, for each sub-block of the set of sub-blocks:
 causing unselected wordlines of the sub-block to be ramped to a pass voltage; 
 causing a selected wordline of the sub-block to be charged to a program voltage; and 
 causing a program verify sense operation to be performed on one or more memory cells of the sub-block to which the selected wordline is connected. 
 
     
     
       10. A method comprising:
 causing, by control logic coupled with a page buffer and a set of sub-blocks in a memory array, a first page of single-level cell (SLC) data to be stored in a cache register of the page buffer, wherein the set of sub-blocks comprise memory cells configured as SLC memory; 
 causing, by the control logic, the first page of the SLC data to be moved from the cache register to a first data register of multiple data registers of the page buffer; 
 causing, by the control logic, a subsequent page of the SLC data to be stored in the cache register; 
 causing, by the control logic, the subsequent page and the first page of the SLC data stored in the cache register and in the first data register, respectively, to be concurrently programmed to the set of sub-blocks, wherein the first page is programmed to a first sub-block and the subsequent page is programmed to a subsequent sub-block of the set of sub-blocks; and 
 causing, by the control logic, operations for programming the set of sub-blocks to be performed in parallel. 
 
     
     
       11. The method of  claim 10 , wherein the set of sub-blocks comprise four sub-blocks of SLC cache and the SLC data comprises four pages. 
     
     
       12. The method of  claim 11 , wherein the subsequent page is a fourth page of the four pages, the method further comprising:
 causing a second page of the SLC data to be stored in the cache register; 
 causing the second page of the SLC data to be moved from the cache register to a second data register of the multiple data registers; 
 causing a third page of the SLC data to be stored in the cache register; and 
 causing the third page of the SLC data to be moved from the cache register to a third data register of the multiple data registers. 
 
     
     
       13. The method of  claim 12 , wherein causing the subsequent page and the first page of the SLC data to be concurrently programmed to the set of sub-blocks further comprises concurrently:
 causing the second page to be programmed to a second sub-block of the set of sub-blocks; 
 causing the third page to be programmed to a third sub-block of the set of sub-blocks; and 
 wherein the subsequent sub-block is a fourth sub-block of the set of sub-blocks. 
 
     
     
       14. The method of  claim 10 , wherein the set of sub-blocks comprise two sub-blocks of SLC cache, the subsequent page is a second page of two pages SLC data, and wherein causing the subsequent page and the first page of the SLC data to be concurrently programmed to the set of sub-blocks comprises cache programming. 
     
     
       15. The method of  claim 10 , wherein the operations for programming the set of sub-blocks further comprise:
 causing charge pump initialization to be performed for the set of sub-blocks; 
 causing a program verify initialization to be performed for the set of sub-blocks; and 
 causing bitlines and wordlines to be discharged during a voltage recovery phase. 
 
     
     
       16. The method of  claim 15 , wherein the operations for programming the set of sub-blocks further comprise selecting one or more bitlines not to be involved with programming. 
     
     
       17. The method of  claim 15 , further comprising:
 causing a selected bitline and a selected source voltage line to be charged to target voltages in preparation for programming a sub-block coupled between the selected bitline and the selected source voltage line; and 
 causing voltages to a select gate line and a select source line to ramp to predetermined voltages, respectively. 
 
     
     
       18. The method of  claim 15 , further comprising serially, for each sub-block of the set of sub-blocks:
 causing unselected wordlines of the sub-block to be ramped to a pass voltage; 
 causing a selected wordline of the sub-block to be charged to a program voltage; and 
 causing a program verify sense operation to be performed on one or more memory cells of the sub-block to which the selected wordline is connected. 
 
     
     
       19. A method comprising:
 causing, by control logic coupled with a page buffer and a set of sub-blocks in a memory array, multiple pages of single-level cell (SLC) data to be sequentially stored within a cache register of the page buffer, wherein the set of sub-blocks comprise memory cells configured as SLC memory; 
 causing, by the control logic, the multiple pages to be sequentially moved from the cache register to respective ones of multiple data registers of the page buffer while retaining a final page of the multiple pages in the cache register; 
 causing, by the control logic, the multiple pages of the SLC data stored in a combination of the cache register and the multiple data registers to be concurrently programmed to the set of sub-blocks, wherein a respective page of the multiple pages is to be programmed to each respective sub-block of the set of sub-blocks; and 
 causing, by the control logic, operations for programming the set of sub-blocks to be performed in parallel. 
 
     
     
       20. The method of  claim 19 , wherein the set of sub-blocks comprise four sub-blocks of SLC cache, the multiple pages comprise four pages of the SLC data, and wherein a first page, a second page, and a third page of the four pages are stored in the multiple data registers while a fourth page of the four pages is retained in the cache register.