Multi-modal refresh of dynamic, random-access memory

Abstract

A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data.

What is claimed is: 
     
       1. An integrated circuit (IC) device comprising:
 stacked and bonded memory dies, each memory die having:
 a first memory-die request interface to a first set of memory banks; and 
 a second memory-die request interface to a second set of memory banks; 
 wherein each of the first and second sets of memory banks include volatile memory cells; 
 
 a controller die bonded to the memory dies, the controller die including:
 a first controller to issue first refresh requests to the first memory-die request interfaces of the bonded memory dies; and 
 a second controller to issue second refresh requests to the second memory-die request interfaces of the bonded memory dies to issue second refresh requests to the second set of memory banks: 
 
 a first refresh-address counter to issue first bank addresses; and 
 a first bank-address demultiplexer having:
 a first demultiplexer input port coupled to the first refresh-address counter to receive the first bank addresses; 
 a first demultiplexer output port coupled to the first and second memory-die request interfaces of a first of the memory dies; and 
 a second demultiplexer output port coupled to the first memory-die request interfaces of the first of the memory dies and a second of the memory dies. 
 
 
     
     
       2. The device of  claim 1 , further comprising:
 a first intra-die request interface coupled to the first and second memory-die request interfaces of a first of the memory dies, the first intra-die request interface to issue first intra-die refresh requests to the first and second sets of memory banks on the first of the memory dies; and 
 a second intra-die request interface coupled to the first and second memory- die request interfaces of a second of the memory dies, the second intra-die request interface to issue second intra-die refresh requests to the first and second sets of memory banks on the second of the memory dies. 
 
     
     
       3. The device of  claim 1 , further comprising:
 a second refresh-address counter to issue second bank addresses; and 
 a second bank-address demultiplexer having:
 a second demultiplexer input port coupled to the first refresh-address counter to receive the first bank addresses; 
 a third demultiplexer output port coupled to the first and second memory-die request interfaces of a second of the memory dies; and 
 a fourth demultiplexer output port coupled to the second memory-die request interfaces of the first of the memory dies and the second of the memory dies. 
 
 
     
     
       4. The device of  claim 3 , wherein the controller die includes the first and second refresh-address counters. 
     
     
       5. The device of  claim 1 , further comprising a mode register coupled to the first bank-address demultiplexer, the mode register to store a value controlling the first bank-address demultiplexer to convey the first bank addresses to one of the first and second demultiplexer output ports. 
     
     
       6. The device of  claim 1 , further comprising:
 a first refresh-address counter to issue first bank addresses to the first memory-die request interface of at least one of the memory dies; 
 a second refresh-address counter to issue second bank addresses to the second memory-die request interface of the at least one of the memory dies; and 
 synchronization logic coupled to the first refresh-address counter and the second refresh-address counter, the synchronization logic to synchronize the first bank addresses with the second bank addresses. 
 
     
     
       7. The device of  claim 6 , wherein:
 the first refresh-address counter to issue the first bank addresses to the first memory-die request interface of the memory dies; and 
 the second refresh-address counter to issue the second bank addresses to the second memory-die request interface of the memory dies. 
 
     
     
       8. The device of  claim 6 , further comprising a control die stacked and bonded to the memory dies, the control die including at least one of the first refresh- address counter and the second refresh-address counter. 
     
     
       9. The device of  claim 8 , the control die further comprising a first processing unit to issue first refresh requests to the first refresh-address counter and a second processing unit to issue second refresh requests to the second refresh-address counter. 
     
     
       10. The device of  claim 9 , wherein each of the first processing unit and the second processing unit includes an array of processing units. 
     
     
       11. An integrated-circuit die comprising:
 a first refresh-address counter to selectively couple to one of a first dynamic, random-access memory and a second dynamic, random-access memory to issue first refresh addresses; 
 a second refresh-address counter selectively coupled to one of the first dynamic, random-access memory and the second dynamic, random-access memory to issue second refresh addresses; and 
 synchronization control circuitry, coupled to the first refresh-address counter and the second refresh-address counter, to synchronize the first refresh addresses with the second refresh addresses. 
 
     
     
       12. The integrated-circuit die of  claim 11 , further comprising:
 a first memory controller selectively coupled to the first refresh-address counter and the second refresh-address counter; and 
 a second memory controller selectively coupled to the first refresh-address counter and the second refresh-address counter. 
 
     
     
       13. The integrated-circuit die of  claim 11 , wherein the first dynamic, random-access memory is integrated on a first die and the second dynamic, random- access memory is integrated on a second die. 
     
     
       14. The integrated-circuit die of  claim 13 , wherein the first counter and the second refresh-address counter are integrated on a third die. 
     
     
       15. The integrated-circuit die of  claim 14 , wherein the first die, the second die, and the third die are bonded in a stack. 
     
     
       16. The integrated-circuit die of  claim 15 , further comprising:
 a first memory controller external to the stack and selectively coupled to the first refresh-address counter and the second refresh-address counter; and 
 a second memory controller integrated on the third die and selectively coupled to the first refresh-address counter and the second refresh-address counter. 
 
     
     
       17. The integrated-circuit die of  claim 16 , wherein the third die comprises an array of processing elements communicatively coupled to the second memory controller. 
     
     
       18. The integrated-circuit die of  claim 17 , wherein the array of processing elements comprises a neural network. 
     
     
       19. A method of refreshing first dynamic, random-access memory and second dynamic, random-access memory, the method comprising:
 conveying first refresh addresses to the first dynamic, random-access memory from a first address counter responsive to a first memory controller; 
 conveying second refresh addresses to the second dynamic, random-access memory from a second address counter responsive to a second memory controller; 
 synchronizing the first refresh addresses with the second refresh addresses; 
 after the synchronizing: 
 conveying the first refresh addresses to the second dynamic, random-access memory from the first address counter responsive to the second memory controller; and 
 conveying the second refresh addresses to the first dynamic, random-access memory from the second address counter responsive to the first memory controller.