Die-to-die and chip-to-chip connectivity monitoring

Abstract

An input/output (I/O) sensor is provided for a multi-IC (Integrated Circuit) module. The I/O sensor includes: a signal input, configured to receive a data signal from an interconnected part of an IC of the multi-IC module; and a time duration measurement circuit, configured to measure a time duration between a first time, at which the data signal is at a first level, and a second time, at which the data signal is at a second level, different from the first level. The sensor may be incorporated into an I/O block, an IC, and/or a multi-IC module.

What is claimed is: 
     
       1. An input/output (I/O) sensor for a multi-IC (Integrated Circuit) module, the I/O sensor comprising:
 a signal input, configured to receive a data signal from an interconnected part of an IC of the multi-IC module; and 
 a time duration measurement circuit, configured to measure a time duration between a first time, at which the data signal is at a first level, and a second time, at which the data signal is at a second level, different from the first level, wherein the time duration measurement circuit comprises:
 a first comparator circuit, configured to generate a first timing signal having an edge when the received data signal is at a first provided level, 
 a second comparator circuit, configured to generate a second timing signal having an edge when the received data signal is at a second provided level, and 
 a timing measurement circuit, configured to receive the first and second timing signals and to measure a time between the edge of the first timing signal and the edge of the second timing signal, wherein the timing measurement circuit comprises:
 delay circuitry, configured to receive the first timing signal and to generate a delayed data signal, the delay circuitry comprising an adjustable delay-line configured to delay an input signal by a set time span, 
 a comparison circuit, configured to generate a comparison signal by comparing the second timing signal with the delayed data signal, and 
 timing measurement processing logic, configured to set the time span of the adjustable delay-line and, based on the comparison signal, identify the time duration. 
 
 
 
     
     
       2. The I/O sensor of  claim 1 , wherein the timing measurement processing logic is configured to:
 for each of a plurality of time spans, set the adjustable delay-line to the respective time span and determine whether the comparison signal for the respective time span indicates a pass or a fail condition; and 
 identify a minimum time span from the plurality of time spans for which the comparison signal indicates a fail condition. 
 
     
     
       3. The I/O sensor of  claim 1 , further comprising offset cancellation circuitry, configured to selectively apply signals derived from the received data signal to the time duration measurement circuit, such that in a first mode, the first provided level is the first level and the second provided level is the second level and in a second mode, the first provided level is the second level and the second provided level is the first level. 
     
     
       4. The I/O sensor of  claim 3 , wherein the offset cancellation circuitry comprises:
 a first multiplexing arrangement, configured to operate in a first mode, in which the first level is provided to the first comparator circuit and the second level is provided to the second comparator circuit or in a second mode, in which the first level is provided to the second comparator circuit and the second level is provided to the first comparator circuit; and 
 a second multiplexing arrangement, configured to operate in a first mode, in which the output of the first comparator circuit is provided as a first timing signal to the timing measurement circuit and the output of the second comparator circuit is provided as a second timing signal to the timing measurement circuit, or in a second mode, in which the output of the second comparator circuit is provided as the first timing signal to the timing measurement circuit and the output of the first comparator circuit is provided as the second timing signal to the timing measurement circuit. 
 
     
     
       5. The I/O sensor of  claim 4 , wherein each of the first and second comparator circuits is configured to operate in a first mode, in which respective comparator circuit generates a respective timing signal having a positive edge when a rising edge of the received data signal is at the respective provided level or in a second mode, in which respective comparator circuit generates a respective timing signal having a positive edge when a falling edge of the received data signal is at the respective provided level. 
     
     
       6. The I/O sensor of  claim 5 , wherein the comparison circuit comprises:
 a first state-element, configured to receive the delayed data signal and to provide a first state-element output based on the delayed data signal and a clock input; 
 a logic arrangement comprising a NOT gate and a NOR gate or OR gate and configured to provide a logic arrangement output based on the first state-element output; and 
 a second state-element, configured to receive the logic arrangement output and to provide a second state-element output based on the logic arrangement output and the clock input; 
 wherein the clock input is based on the second timing signal and wherein the local arrangement is configured to receive the first state-element output at the NOT gate, provide an output of the NOT gate as a first input to the NOR gate and the second state-element output at a second input to the NOR, the logic arrangement output being an output of the NOR gate. 
 
     
     
       7. The I/O sensor of  claim 5 , wherein the clock input is the second timing signal or a delayed version of the second timing signal. 
     
     
       8. The I/O sensor of  claim 5 , wherein the comparison circuit further comprises:
 a third state-element, configured to receive a low logic level at a third state-element data input and to provide a third state-element output based on the received low logic level and the clock input, the third state-element further configured to receive a reset signal at a third state-element set state input; 
 a fourth state-element, configured to receive a signal based on the third state-element output at a fourth state-element data input and to provide a fourth state-element output based on the signal received at the fourth state-element data input and the clock input, the fourth state-element further configured to receive the reset signal at a fourth state-element set state input; and 
 wherein the first state-element is further configured to receive the reset signal at a first state-element set state input and the second state-element is further configured to receive a signal based on the fourth state-element output at a second state-element reset state input. 
 
     
     
       9. The I/O sensor of  claim 3 , further comprising:
 sensor processing logic, configured to control the offset cancellation circuitry and the time duration measurement circuit to measure a first time duration in the first mode of the offset cancellation circuitry and a second time duration in the second mode of the offset cancellation circuitry and to determine a signal time duration based on the measured first and second time durations. 
 
     
     
       10. The I/O sensor of  claim 1 , wherein the time duration measurement circuit is further configured to measure a time duration between the second time, at which the data signal is at the second level and a third time, at which the data signal is at a third level. 
     
     
       11. The I/O sensor of  claim 1 , further comprising:
 sensor processing logic, configured to determine a slew rate for the data signal from the time duration measured by the time duration measurement circuit. 
 
     
     
       12. A non-transitory computer readable medium having stored thereon a computer-readable encoding of an I/O sensor, the computer-readable encoding of the I/O sensor comprising:
 a signal input, configured to receive a data signal from an interconnected part of an IC of the multi-IC module; and 
 a time duration measurement circuit, configured to measure a time duration between a first time, at which the data signal is at a first level, and a second time, at which the data signal is at a second level, different from the first level, wherein the time duration measurement circuit comprises:
 a first comparator circuit, configured to generate a first timing signal having an edge when the received data signal is at a first provided level, 
 a second comparator circuit, configured to generate a second timing signal having an edge when the received data signal is at a second provided level, and 
 a timing measurement circuit, configured to receive the first and second timing signals and to measure a time between the edge of the first timing signal and the edge of the second timing signal, wherein the timing measurement circuit comprises:
 delay circuitry, configured to receive the first timing signal and to generate a delayed data signal, the delay circuitry comprising an adjustable delay-line configured to delay an input signal by a set time span, 
 a comparison circuit, configured to generate a comparison signal by comparing the second timing signal with the delayed data signal, and 
 timing measurement processing logic, configured to set the time span of the adjustable delay-line and, based on the comparison signal, identify the time duration. 
 
 
 
     
     
       13. The non-transitory computer readable medium of  claim 12 , wherein the timing measurement processing logic is configured to:
 for each of a plurality of time spans, set the adjustable delay-line to the respective time span and determine whether the comparison signal for the respective time span indicates a pass or a fail condition; and 
 identify a minimum time span from the plurality of time spans for which the comparison signal indicates a fail condition. 
 
     
     
       14. The non-transitory computer readable medium of  claim 12 , wherein the computer-readable encoding of the I/O sensor further comprises offset cancellation circuitry, configured to selectively apply signals derived from the received data signal to the time duration measurement circuit, such that in a first mode, the first provided level is the first level and the second provided level is the second level and in a second mode, the first provided level is the second level and the second provided level is the first level. 
     
     
       15. The non-transitory computer readable medium of  claim 14 , wherein the offset cancellation circuitry comprises:
 a first multiplexing arrangement, configured to operate in a first mode, in which the first level is provided to the first comparator circuit and the second level is provided to the second comparator circuit or in a second mode, in which the first level is provided to the second comparator circuit and the second level is provided to the first comparator circuit; and 
 a second multiplexing arrangement, configured to operate in a first mode, in which the output of the first comparator circuit is provided as a first timing signal to the timing measurement circuit and the output of the second comparator circuit is provided as a second timing signal to the timing measurement circuit, or in a second mode, in which the output of the second comparator circuit is provided as the first timing signal to the timing measurement circuit and the output of the first comparator circuit is provided as the second timing signal to the timing measurement circuit. 
 
     
     
       16. The non-transitory computer readable medium of  claim 15 , wherein each of the first and second comparator circuits is configured to operate in a first mode, in which respective comparator circuit generates a respective timing signal having a positive edge when a rising edge of the received data signal is at the respective provided level or in a second mode, in which respective comparator circuit generates a respective timing signal having a positive edge when a falling edge of the received data signal is at the respective provided level. 
     
     
       17. The non-transitory computer readable medium of  claim 16 , wherein the comparison circuit comprises:
 a first state-element, configured to receive the delayed data signal and to provide a first state-element output based on the delayed data signal and a clock input; 
 a logic arrangement comprising a NOT gate and a NOR gate or OR gate and configured to provide a logic arrangement output based on the first state-element output; and 
 a second state-element, configured to receive the logic arrangement output and to provide a second state-element output based on the logic arrangement output and the clock input; 
 wherein the clock input is based on the second timing signal and wherein the local arrangement is configured to receive the first state-element output at the NOT gate, provide an output of the NOT gate as a first input to the NOR gate and the second state-element output at a second input to the NOR, the logic arrangement output being an output of the NOR gate. 
 
     
     
       18. The non-transitory computer readable medium of  claim 16 , wherein the clock input is the second timing signal or a delayed version of the second timing signal. 
     
     
       19. The non-transitory computer readable medium of  claim 16 , wherein the comparison circuit further comprises:
 a third state-element, configured to receive a low logic level at a third state-element data input and to provide a third state-element output based on the received low logic level and the clock input, the third state-element further configured to receive a reset signal at a third state-element set state input; 
 a fourth state-element, configured to receive a signal based on the third state-element output at a fourth state-element data input and to provide a fourth state-element output based on the signal received at the fourth state-element data input and the clock input, the fourth state-element further configured to receive the reset signal at a fourth state-element set state input; and 
 wherein the first state-element is further configured to receive the reset signal at a first state-element set state input and the second state-element is further configured to receive a signal based on the fourth state-element output at a second state-element reset state input. 
 
     
     
       20. The non-transitory computer readable medium of  claim 14 , wherein the computer-readable encoding of the I/O sensor further comprises:
 sensor processing logic, configured to control the offset cancellation circuitry and the time duration measurement circuit to measure a first time duration in the first mode of the offset cancellation circuitry and a second time duration in the second mode of the offset cancellation circuitry and to determine a signal time duration based on the measured first and second time durations. 
 
     
     
       21. The non-transitory computer readable medium of  claim 12 , wherein
 the time duration measurement circuit is further configured to measure a time duration between the second time, at which the data signal is at the second level and a third time, at which the data signal is at a third level. 
 
     
     
       22. The non-transitory computer readable medium of  claim 12 , wherein the computer-readable encoding of the I/O sensor further comprises:
 sensor processing logic, configured to determine a slew rate for the data signal from the time duration measured by the time duration measurement circuit.