Memory device and method of controlling row hammer

Abstract

A method of controlling a row hammer swaps a first address entry with a second address entry having the smallest second access number and randomly swaps the first address entry with a third address entry having a third access number which is not the greatest value, in an address table representing a correlation between an address entry accessed during a row hammer monitoring time frame and an access number, thereby preventing a hacker-pattern row hammer aggression from being easily performed.

What is claimed is: 
     
       1. A memory device comprising:
 a memory cell array including a plurality of memory cell rows; 
 a control logic circuit configured to monitor a row address with respect to a memory cell row from among the plurality of memory cell rows during a row hammer monitoring time frame and store the row address as an address entry in an address table in which an access number of the address entry is stored; and 
 a refresh control circuit configured to refresh a memory cell row physically adjacent to another memory cell row corresponding to an address entry having the greatest access number stored in the address table during the row hammer monitoring time frame, wherein 
 the control logic circuit performs a counter-based flattening operation and a random swap operation on the address entry stored in the address table. 
 
     
     
       2. The memory device of  claim 1 , wherein the control logic circuit receives a first row address and stores the first row address as a first address entry having a first access number in a free space of the address table. 
     
     
       3. The memory device of  claim 2 , wherein the first access number is set to 1. 
     
     
       4. The memory device of  claim 1 , wherein:
 the control logic circuit receives a first row address, selects a second address entry having a second access number from the address table when there is no free space in the address table, and performs a first swap operation of swapping a first address entry with the second address entry, and 
 the second access number is the smallest access number in the address table. 
 
     
     
       5. The memory device of  claim 4 , wherein the control logic circuit performs the counter-based flattening operation by setting the access number of the first address entry to a first value obtained by incrementing the second access number by 1. 
     
     
       6. The memory device of  claim 5 , wherein:
 the control logic circuit randomly selects a third address entry having a third access number from the address table and performs a second swap operation related to the first address entry and the third address entry, and 
 the third access number is not the greatest value in the address table. 
 
     
     
       7. The memory device of  claim 6 , wherein the second swap operation is a random swap operation of swapping the access number of the first value of the first address entry with the third access number. 
     
     
       8. The memory device of  claim 6 , wherein the second swap operation is a random swap operation of swapping the first address entry with the third address entry. 
     
     
       9. The memory device of  claim 1 , wherein the control logic circuit resets the address table to a free space after the row hammer monitoring time frame elapses. 
     
     
       10. The memory device of  claim 1 , wherein the control logic circuit uses a basic refresh rate time specified in the memory device as the row hammer monitoring time frame. 
     
     
       11. A control logic circuit comprising:
 a logic circuit indicating a correlation between a row address accessed during a row hammer monitoring time frame and an access number and including an address table storing a first address entry corresponding to a first row address and a first access number; 
 a first swap circuit configured to select a second address entry having a second access number, which is the smallest access number in the address table, from the address table and perform a first swap operation of swapping the first address entry with the second address entry; and 
 a second swap circuit configured to select a third address entry having a third access number from the address table and perform a second swap operation related to the first address entry and the third address entry, wherein 
 the third access number is not the greatest value in the address table. 
 
     
     
       12. The control logic circuit of  claim 11 , wherein the control logic circuit further comprises a random number generator configured to randomly select the third address entry from the address table. 
     
     
       13. The control logic circuit of  claim 11 , wherein the first swap circuit sets a first value, obtained by incrementing the second access number by 1, as an access number of the first address entry when swapping the second address entry with the first address entry and performs a flattening operation on address entries stored in the address table. 
     
     
       14. The control logic circuit of  claim 13 , wherein the second swap circuit performs a random swap operation of swapping the access number of the first value of the first address entry with the third access number. 
     
     
       15. The control logic circuit of  claim 13 , wherein the second swap circuit performs a random swap operation of swapping the first address entry with the third address entry. 
     
     
       16. The control logic circuit of  claim 11 , wherein the logic circuit resets the address table to a free space after the row hammer monitoring time frame elapses. 
     
     
       17. The control logic circuit of  claim 11 , wherein a basic refresh rate defined in a memory device including the control logic circuit is used as the row hammer monitoring time frame. 
     
     
       18. A method of operating a memory device including a plurality of memory cell rows, the method comprising:
 monitoring a first row address with respect to a first memory cell row from among the plurality of memory cell rows during a row hammer monitoring time frame; 
 storing a first address entry corresponding to the first row address and a first access number in an address table; 
 selecting a second address entry having a second access number, which is the smallest access number in the address table, from the address table; 
 performing a first swap operation related to the first address entry and the second address entry; 
 randomly selecting a third address entry having a third access number, which does not have the greatest value in the address table, from the address table; 
 performing a second swap operation related to the first address entry and the third address entry; and 
 refreshing a memory cell row physically adjacent to another memory cell row corresponding to an address entry having the greatest access number stored in the address table during the row hammer monitoring time frame. 
 
     
     
       19. The method of  claim 18 , wherein the storing of the first address entry corresponding to the first row address and the first access number in the address table further comprises storing the first address entry having the first access number in a free space of the address table. 
     
     
       20. The method of  claim 19 , wherein the first access number is set to 1.