Pixel, driver and display device having the same

Abstract

A display device includes: a pixel electrically connected to a data line, a write scan line, an initialization scan line, a compensation scan line, a transmission control line, and an emission control line; a first driving circuit configured to provide a write scan signal to the write scan line and a second driving circuit configured to receive a plurality of clock signals, each of which has a time duration of one unit horizontal period and provide an initialization scan signal, a compensation scan signal, a transmission control signal, and an emission control signal to the initialization scan line, the compensation scan line, the transmission control line, and the emission control line, respectively. Each of the initialization scan signal and the compensation scan signal has an activation interval of one unit horizontal periods or more.

What is claimed is: 
     
       1. A display device comprising:
 a pixel electrically connected to a data line, a write scan line, an initialization scan line, a compensation scan line, a transmission control line, and an emission control line and including a pixel circuit and a display element; 
 a first driving circuit configured to provide a write scan signal to the write scan line; and 
 a second driving circuit configured to: 
 receive a plurality of clock signals, each of which has a time duration of one unit horizontal period, and 
 provide an initialization scan signal, a compensation scan signal, a transmission control signal, and an emission control signal to the initialization scan line, the compensation scan line, the transmission control line, and the emission control line, respectively, 
 wherein each of the initialization scan signal and the compensation scan signal has an activation interval of two unit horizontal periods or more, 
 wherein the pixel circuit includes: 
 a first transistor including a gate electrode connected to a first node, a first electrode, and a second electrode connected to a second node; 
 a second transistor connected to the data line, an operation of the second transistor being controlled by the write scan signal provided to the write scan line; and 
 a third transistor connected between the second transistor and a third node, an operation of the third transistor being controlled by the transmission control signal provided to the transmission control line and different from the write scan signal. 
 
     
     
       2. The display device of  claim 1 , wherein the initialization scan signal includes a first initialization activation interval having a first horizontal period and a second initialization activation interval having a second horizontal period greater than or equal to the first horizontal period, and
 wherein the compensation scan signal includes a first compensation activation interval having a third horizontal period and a second compensation activation interval having a fourth horizontal period greater than or equal to the third horizontal period. 
 
     
     
       3. The display device of  claim 2 , wherein each of the first horizontal period and the third horizontal period has a time duration of one unit horizontal period, and each of the second horizontal period and the fourth horizontal period has a time duration of two unit horizontal periods or more. 
     
     
       4. The display device of  claim 2 , wherein each of the first horizontal period, the second horizontal period, the third horizontal period, and the fourth horizontal period has a time duration of two unit horizontal periods or more. 
     
     
       5. The display device of  claim 1 ,
 wherein the pixel circuit further includes:
 a first capacitor connected between the first node and the third node; and 
 a second capacitor connected between the third node and a driving voltage line. 
 
 
     
     
       6. The display device of  claim 5 , wherein the pixel circuit further includes:
 a fourth transistor connected between the first node and the second node, an operation of the fourth transistor being controlled by the compensation scan signal provided to the compensation scan line; 
 a fifth transistor connected between the first node and a first initialization voltage line, an operation of the fifth transistor being controlled by the initialization scan signal provided to the initialization scan line; 
 a sixth transistor connected between the second node and the display element, an operation of the sixth transistor being controlled by the emission control signal provided to the emission control line; and 
 a seventh transistor connected between the display element and a second initialization voltage line, an operation of the seventh transistor being controlled by the write scan signal provided to the write scan line. 
 
     
     
       7. The display device of  claim 6 , wherein the pixel circuit further includes:
 an eighth transistor connected between the third node and a reference voltage line, an operation of the eighth transistor being controlled by the compensation scan signal provided to the compensation scan line, 
 wherein each of the first transistor, the second transistor, the sixth transistor, and the seventh transistor is a P-type thin film transistor having a silicon semiconductor layer, and 
 wherein each of the third transistor, the fourth transistor, the fifth transistor, and the eighth transistor is an N-type thin film transistor having an oxide semiconductor layer. 
 
     
     
       8. The display device of  claim 7 , wherein the pixel circuit further includes:
 a ninth transistor connected between the first electrode of the first transistor and the driving voltage line; and 
 a tenth transistor connected between the first electrode of the first transistor and a bias voltage line, an operation of the tenth transistor being controlled by the write scan signal provided to the write scan line, and 
 wherein each of the ninth transistor and the tenth transistor is the P-type thin film transistor having the silicon semiconductor layer. 
 
     
     
       9. The display device of  claim 6 , wherein the pixel circuit further includes:
 an eighth transistor connected between the first electrode of the first transistor and the third node, an operation of the eighth transistor being controlled by the compensation scan signal provided to the compensation scan line. 
 
     
     
       10. The display device of  claim 5 , wherein the pixel circuit is configured to operate in a write cycle interval and a hold cycle interval,
 wherein, in the write cycle interval, a data signal provided through the data line is delivered to the pixel circuit, and 
 wherein, in the hold cycle interval, an anode of the display element is initialized. 
 
     
     
       11. The display device of  claim 10 , wherein the write scan signal includes a first write activation interval overlapping the write cycle interval and a second write activation interval overlapping the hold cycle interval, and
 wherein the data signal is delivered to the pixel in the first write activation interval, and the anode of the display element is initialized in the second write activation interval. 
 
     
     
       12. The display device of  claim 11 , wherein each of the first write activation interval and the second write activation interval is one unit horizontal period or more. 
     
     
       13. The display device of  claim 11 , wherein a length of the first write activation interval is different from a length of the second write activation interval. 
     
     
       14. The display device of  claim 11 , wherein the transmission control signal includes a transmission activation interval, and the transmission activation interval overlaps the first write activation interval. 
     
     
       15. The display device of  claim 14 , wherein the transmission activation interval of the transmission control signal does not overlap the hold cycle interval. 
     
     
       16. The display device of  claim 1 , wherein the second driving circuit includes:
 a first sub-driving circuit configured to receive first clock signals and to output the emission control signal; 
 a second sub-driving circuit configured to receive second clock signals and to output the initialization scan signal and the compensation scan signal; and 
 a third sub-driving circuit configured to receive third clock signals and to output the transmission control signal, 
 wherein a time duration of each of the first clock signals is one unit horizontal period, 
 wherein a time duration of each of the second clock signals is one unit horizontal period, and 
 wherein a time duration of each of the third clock signals is one unit horizontal period. 
 
     
     
       17. A display device comprising:
 a pixel electrically connected to a data line, a write scan line, an initialization scan line, a compensation scan line, a transmission control line, and an emission control line and including a pixel circuit and a display element; and 
 a driving circuit configured to provide a write scan signal, an initialization scan signal, a compensation scan signal, a transmission control signal, and an emission control signal to the write scan line, the initialization scan line, the compensation scan line, the transmission control line, and the emission control line, respectively, 
 wherein the initialization scan signal includes a first initialization activation interval having a first horizontal period and a second initialization activation interval having a second horizontal period greater than or equal to the first horizontal period, 
 wherein the compensation scan signal includes a first compensation activation interval having a third horizontal period and a second compensation activation interval having a fourth horizontal period greater than or equal to the third horizontal period, and 
 wherein each of the second horizontal period and the fourth horizontal period has a time duration of two unit horizontal periods or more. 
 
     
     
       18. The display device of  claim 17 , wherein the driving circuit includes:
 a first sub-driving circuit configured to receive first clock signals and to output the emission control signal; 
 a second sub-driving circuit configured to receive second clock signals and to output the initialization scan signal and the compensation scan signal; 
 a third sub-driving circuit configured to receive third clock signals and to output the transmission control signal; and 
 a scan driving circuit configured to receive fourth clock signals and to output the write scan signal. 
 
     
     
       19. The display device of  claim 17 , wherein the pixel circuit is configured to operate in a write cycle interval and a hold cycle interval,
 wherein the write scan signal includes a first write activation interval overlapping the write cycle interval and a second write activation interval overlapping the hold cycle interval, and 
 wherein a data signal is delivered to the pixel in the first write activation interval, and an anode of the display element is initialized in the second write activation interval. 
 
     
     
       20. The display device of  claim 19 , wherein the transmission control signal includes a transmission activation interval, and
 wherein the transmission activation interval overlaps the first write activation interval and does not overlap the hold cycle interval. 
 
     
     
       21. A display device comprising:
 a pixel electrically connected to a data line, a write scan line, an initialization scan line, a compensation scan line, a transmission control line, and an emission control line and including a pixel circuit and a display element, wherein the pixel circuit includes a plurality of transistors and a capacitor; and 
 a driving circuit configured to provide a write scan signal, an initialization scan signal, a compensation scan signal, a transmission control signal, and an emission control signal to the write scan line, the initialization scan line, the compensation scan line, the transmission control line, and the emission control line, respectively, 
 wherein the pixel circuit is configured to operate in a write cycle interval and a hold cycle interval, 
 wherein the write scan signal includes a first write activation interval overlapping the write cycle interval and a second write activation interval overlapping the hold cycle interval, 
 wherein, in the first write activation interval, a data signal provided through the data line is delivered to the capacitor, and an anode of the display element is primarily initialized, and 
 wherein, in the second write activation interval, the data signal is blocked from being delivered to the capacitor, and the anode of the display element is secondarily initialized. 
 
     
     
       22. A driver comprising:
 a first driving circuit configured to provide a write scan signal to a write scan line connected to a pixel; and 
 a second driving circuit configured to: 
 receive a plurality of clock signals, each of which has a time duration of one unit horizontal period; and 
 provide an initialization scan line, a compensation scan line, a transmission control line, and an emission control line, which are connected to the pixel, with an initialization scan signal having an activation interval of two unit horizontal periods or more, a compensation scan signal having an activation interval of two unit horizontal periods or more, a transmission control signal, and an emission control signal, respectively. 
 
     
     
       23. The driver of  claim 22 , wherein the initialization scan signal includes a first initialization activation interval having a first horizontal period and a second initialization activation interval having a second horizontal period greater than or equal to the first horizontal period, and
 wherein the compensation scan signal includes a first compensation activation interval having a third horizontal period and a second compensation activation interval having a fourth horizontal period greater than or equal to the third horizontal period. 
 
     
     
       24. The driver of  claim 22 , wherein the write scan signal includes a first write activation interval overlapping a write cycle interval and a second write activation interval overlapping a hold cycle interval,
 wherein the transmission control signal includes a transmission activation interval, and 
 wherein the transmission activation interval overlaps the first write activation interval and does not overlap the hold cycle interval. 
 
     
     
       25. The driver of  claim 22 , wherein the second driving circuit includes:
 a first sub-driving circuit configured to receive first clock signals and to output the emission control signal; 
 a second sub-driving circuit configured to receive second clock signals and to output the initialization scan signal and the compensation scan signal; and 
 a third sub-driving circuit configured to receive third clock signals and to output the transmission control signal, 
 wherein a time duration of each of the first clock signals is one unit horizontal period, 
 wherein a time duration of each of the second clock signals is one unit horizontal period, and 
 wherein a time duration of each of the third clock signals is one unit horizontal period. 
 
     
     
       26. A pixel comprising:
 a display element; and 
 a pixel circuit connected to the display element, 
 wherein the pixel circuit includes:
 a first transistor including a gate electrode connected to a first node, a first electrode, and a second electrode connected to a second node; 
 a first capacitor connected between the first node and a third node; 
 a second capacitor connected between the third node and a driving voltage line; 
 a second transistor connected to a data line, wherein an operation of the second transistor is controlled by a write scan signal provided to a write scan line; and 
 a third transistor connected between the second transistor and the third node, an operation of the third transistor being controlled by a transmission control signal provided to a transmission control line and different from the write scan signal. 
 
 
     
     
       27. The pixel of  claim 26 , wherein the pixel circuit further includes:
 a fourth transistor connected between the first node and the second node, an operation of the fourth transistor being controlled by a compensation scan signal provided to a compensation scan line; 
 a fifth transistor connected between the first node and a first initialization voltage line, an operation of the fifth transistor being controlled by an initialization scan signal provided to an initialization scan line; 
 a sixth transistor connected between the second node and the display element, an operation of the sixth transistor being controlled by an emission control signal provided to an emission control line; and 
 a seventh transistor connected between the display element and a second initialization voltage line, an operation of the seventh transistor being controlled by the write scan signal provided to the write scan line. 
 
     
     
       28. The pixel of  claim 27 , wherein the pixel circuit includes:
 an eighth transistor connected between the third node and a reference voltage line, an operation of the eighth transistor being controlled by the compensation scan signal provided to the compensation scan line, 
 wherein each of the first transistor, the second transistor, the sixth transistor, and the seventh transistor is a P-type thin film transistor having a silicon semiconductor layer, and 
 wherein each of the third transistor, the fourth transistor, the fifth transistor, and the eighth transistor is an N-type thin film transistor having an oxide semiconductor layer. 
 
     
     
       29. The pixel of  claim 28 , wherein the pixel circuit includes:
 a ninth transistor connected between the first electrode of the first transistor and the driving voltage line; and 
 a tenth transistor connected between the first electrode of the first transistor and a bias voltage line, an operation of the tenth transistor being controlled by the write scan signal provided to the write scan line, and 
 wherein each of the ninth transistor and the tenth transistor is the P-type thin film transistor having the silicon semiconductor layer. 
 
     
     
       30. The pixel of  claim 27 , wherein the pixel circuit includes:
 an eighth transistor connected between the first electrode of the first transistor and the third node, an operation of the eighth transistor being controlled by the compensation scan signal provided to the compensation scan line.