Methods and systems for controlling frequency variation for a PLL reference clock

Abstract

This application is directed to frequency controlling in an electronic device (e.g., a retimer of a data link). The electronic device includes a selector, a clock generated, and a controller. The selector selects one of a first reference signal and a second reference signal as an input signal having an input phase. The clock generator receives the input signal and generates a periodic signal with reference to the input signal, and the periodic signal has an output phase that matches the input phase of the input signal. While the first reference signal is selected as the input signal, the controller determines whether the second reference signal is in a temporal range in which the second reference signal reaches a peak frequency and controls the selector to select the second reference signal as the input signal in accordance with a determination that the second reference signal is in the temporal range.

What is claimed is: 
     
       1. An electronic device, comprising:
 a selector configured to select one of a first reference signal and a second reference signal as an input signal having an input phase; 
 a clock generator coupled to the selector, the clock generator being configured to receive the input signal and generate a periodic signal with reference to the input signal, the periodic signal having an output phase that matches the input phase of the input signal; and 
 a controller coupled to the selector, the controller configured to, while the first reference signal is selected as the input signal:
 determine, within a cycle of the second reference signal, whether the second reference signal is in a predetermined temporal range in which the second reference signal reaches a peak frequency, wherein the temporal range is less than a period of the second reference signal; and 
 in accordance with a determination that the second reference signal is in the temporal range, control the selector to select the second reference signal as the input signal. 
 
 
     
     
       2. The electronic device of  claim 1 , wherein determining whether the second reference signal is in the temporal range further comprises:
 while the first reference signal is selected as the input signal, determining that a frequency of the second reference signal is rising towards the peak frequency during the temporal range, wherein the selector is controlled by the controller to select the second reference signal in place of the first reference signal in accordance with a determination that the frequency of the second reference signal is rising towards the peak frequency in the temporal range. 
 
     
     
       3. The electronic device of  claim 1 , wherein the controller is further configured to:
 receive a system reset signal; and 
 while the first reference signal is selected as the input signal, determine whether the system reset signal is enabled, wherein the selector is controlled by the controller to select the second reference signal in place of the first reference signal in accordance with a determination that the system reset signal is disabled and a determination that the second reference signal is in the temporal range. 
 
     
     
       4. The electronic device of  claim 1 , wherein:
 the first reference signal has a first frequency that is substantially stable; and 
 the peak frequency is equal to the first frequency. 
 
     
     
       5. The electronic device of  claim 4 , wherein the second reference signal has a second frequency that varies periodically between the peak frequency and a down-spreading frequency. 
     
     
       6. The electronic device of  claim 5 , wherein:
 the period of the second reference signal is a spreading period; 
 the second frequency of the second reference signal varies with a spreading frequency corresponding to the spreading period; and 
 the controller is configured to:
 monitor an overshoot of an output frequency of the periodic signal; and 
 dynamically adjust the temporal range based on the overshoot of the output frequency of the periodic signal. 
 
 
     
     
       7. The electronic device of  claim 6 , wherein:
 the output frequency of the periodic signal is substantially equal to 20 GHz; 
 the first frequency of the first reference signal is substantially equal to 25 MHz; 
 the spreading frequency is substantially equal to 1.25 MHz; 
 the second frequency of the second reference signal varies, periodically with the spreading frequency, between 25 MHz and 23.75 MHz; and 
 the temporal range is less than 0.5% of the spreading period. 
 
     
     
       8. The electronic device of  claim 1 , wherein the clock generator further comprises a phase lock loop (PLL), the PLL further comprising:
 a PLL frequency or phase comparator configured to receive the input signal and a feedback clock and generate a PLL comparison signal; 
 a loop filter coupled to the PLL frequency or phase comparator, the PLL configured to generate a DC difference voltage based on the PLL comparison signal; 
 a voltage controlled oscillator (VCO) coupled to the loop filter, the VCO configured to generate the periodic signal based on the DC difference voltage; and 
 a feedback path coupled to the VCO and PLL frequency or phase comparator, the feedback path configured to convert the periodic signal to the feedback clock and feed the feedback clock to the PLL frequency or phase comparator. 
 
     
     
       9. The electronic device of  claim 8 , wherein the PLL further comprises:
 a charge pump circuit coupled to the loop filter, the charge pump circuit configured to control a variation rate of the DC difference voltage, such that in response to the input signal being switched from the first reference signal to the second reference signal, an overshoot on an output frequency of the periodic signal is less than a predefined portion of the output frequency. 
 
     
     
       10. The electronic device of  claim 1 , wherein the controller further comprises:
 a frequency or phase difference detector configured to detect a frequency or phase difference between the second reference signal and a third reference signal; 
 an integrator coupled to the frequency or phase difference detector, the integrator being configured to generate a lock voltage that increases in response to detection of the frequency or phase difference of the second and third reference signals; 
 a comparator coupled to the integrator, the comparator being configured to compare the lock voltage with a lock threshold associated with the temporal range; and 
 a lock latch coupled to the comparator, the lock latch being configured to, in accordance with a determination that the lock voltage exceeds the lock threshold, enable a lock signal for controlling the selector to select the second reference signal as the input signal. 
 
     
     
       11. The electronic device of  claim 10 , wherein the frequency or phase difference detector includes a frequency difference detector configured to detect a frequency difference between the second and third reference signals, and the integrator includes an OR logic coupled to the frequency difference detector to enable integration within the integrator. 
     
     
       12. The electronic device of  claim 10 , wherein the frequency or phase difference detector includes the phase difference detector configured to detect a phase difference between the second and third reference signals, and the integrator includes an OR logic coupled to the phase difference detector to enable integration within the integrator. 
     
     
       13. The electronic device of  claim 10 , wherein the clock generator is further configured to divide the periodic signal to generate the third reference signal, and the controller is configured to receive the third reference signal from the clock generator. 
     
     
       14. The electronic device of  claim 10 , wherein the controller is configured to:
 monitor an overshoot of an output frequency of the periodic signal; and 
 dynamically adjust the lock threshold based on the overshoot of the output frequency of the periodic signal. 
 
     
     
       15. The electronic device of  claim 1 , wherein the controller further comprises:
 a frequency or phase difference detector configured to detect a frequency or phase difference between the second reference signal and a third reference signal; 
 an integrator coupled to the frequency difference detector, the integrator being configured to generate a lock voltage that decreases from a voltage rail in response to detection of the frequency or phase difference of the second and third reference signals; 
 a comparator coupled to the integrator, the comparator being configured to compare the lock voltage with a lock threshold associated with the temporal range; and 
 a lock latch coupled to the comparator, the lock latch being configured to, in accordance with a determination that the lock voltage drops below the lock threshold, enable a lock signal for controlling the selector to select the second reference signal as the input signal. 
 
     
     
       16. The electronic device of  claim 1 , wherein in response to the input signal being switched from the first reference signal to the second reference signal, the periodic signal has an overshoot on an output frequency of the periodic signal, and the overshoot is less than a predefined portion of the peak frequency. 
     
     
       17. The electronic device of  claim 1 , wherein the selector, clock generator, and controller are integrated on a single substrate. 
     
     
       18. The electronic device of  claim 1 , further comprising a data link having a retimer, wherein the retimer includes a transmitter portion, a receiver portion, the selector, the clock generator, and the controller, and is configured to:
 operate at a link training mode and a data transmission mode; 
 reconfigure the receiver or transmitter portion based on the periodic signal that is generated from the first reference signal in the link training mode; and 
 communicate data in synchronization with the periodic signal that is generated from the second reference signal in the data transmission mode. 
 
     
     
       19. A clock generation method, comprising:
 selecting an input signal from a first reference signal and a second reference signal; 
 generating a periodic signal with reference to the input signal, the periodic signal having an output phase that matches an input phase of the input signal; and 
 while selecting the first reference signal as the input signal:
 determining, within a cycle of the second reference signal, whether the second reference signal is in a predetermined temporal range in which the second reference signal reaches a peak frequency, wherein the temporal range is less than a period of the second reference signal; and 
 in accordance with a determination that the second reference signal is in the temporal range, switching the input signal from the first reference signal to the second reference signal. 
 
 
     
     
       20. A method, comprising:
 providing a selector to select an input signal from a first reference signal and a second reference signal; 
 providing a clock generator configured to receive the input signal and generate a periodic signal with reference to the input signal, the periodic signal having an output phase that matches an input phase of the input signal; and 
 providing a controller coupled to the clock generator, the controller configured to, while the first reference signal is selected as the input signal:
 determine, within a cycle of the second reference signal, whether the second reference signal is in a predetermined temporal range in which the second reference signal reaches a peak frequency, wherein the temporal range is less than a period of the second reference signal; and 
 in accordance with a determination that the second reference signal is in the temporal range, switch the input signal from the first reference signal to the second reference signal.