Probe card for device under test

Abstract

A probe card with a voltage terminal configured to be coupled to a voltage supply and a current terminal configured to be coupled to a current supply. The voltage terminal and the current terminal are configured to be coupled to an input node of a device under test (DUT) field effect transistor (FET) through probe needles. The probe card has an overlap resistor capacitor (RC) element coupled to the input node. The probe card includes an analog to digital (ADC) voltage capture module configured to be coupled to the input node of the DUT FET and to an output node of the DUT FET through the probe needles. The probe card has a resistive element configured to be coupled to the output node of the DUT FET through the probe needles and to an electrically neutral node and an ADC current capture module coupled in parallel to the resistive element.

What is claimed is: 
     
       1. A probe card comprising:
 a voltage terminal configured to be coupled to a voltage supply; 
 a current terminal configured to be coupled to a current supply, wherein the voltage terminal and the current terminal are configured to be coupled to an input node of a device under test (DUT) field effect transistor (FET) through probe needles; 
 a overlap resistor capacitor (RC) element coupled to the input node of the DUT FET and to an electrically neutral node; 
 an analog to digital (ADC) voltage capture module configured to be coupled to the input node of the DUT FET and to an output node of the DUT FET through the probe needles; 
 a resistive element configured to be coupled to the output node of the DUT FET through the probe needles and to an electrically neutral node; and 
 an ADC current capture module coupled in parallel to the resistive element. 
 
     
     
       2. The probe card of  claim 1 , wherein the DUT FET is embedded in a wafer. 
     
     
       3. The probe card of  claim 2 , wherein the DUT FET is a gallium nitride (GaN) FET. 
     
     
       4. The probe card of  claim 3 , wherein the ADC voltage capture module is configured to capture at least 20 million voltage measurements per second and the ADC current capture module is configured to capture at least 50 million current measurements per second. 
     
     
       5. The probe card of  claim 4 , wherein the ADC voltage capture module and the ADC current capture module are configured to provide data to a data acquisition system of an automatic test equipment (ATE) to measure a drain to source on resistance of the DUT FET. 
     
     
       6. The probe card of  claim 5 , wherein the ATE further comprises:
 an ATE head; 
 a prober interface board (PIB) mounted on the ATE head, the PIB comprising the voltage supply and the current supply, wherein the probe card is mounted on the PIB, and the probe card overlies the wafer. 
 
     
     
       7. The probe card of  claim 6 , wherein the wafer is mounted on a chuck of a wafer prober that is moveable along an axis and the probe needles extend perpendicularly from the probe card to the wafer. 
     
     
       8. The probe card of  claim 1 , wherein the voltage supply supplies a voltage of at least 1 kilovolt (kV). 
     
     
       9. The probe card of  claim 1 , wherein the overlap RC element injects current to the input node of the DUT FET in response to the DUT FET switching from a cutoff region to a linear region or saturation region. 
     
     
       10. The probe card of  claim 9 , wherein the current supply injects a current into the input node of the DUT FET in response to depletion of the current injected by the overlap RC element. 
     
     
       11. The probe card of  claim 1 , wherein a driver is configured to be coupled to a control node of the DUT FET through the probe needles. 
     
     
       12. A probe card comprising:
 a voltage terminal configured to be coupled to a voltage supply; 
 a current terminal configured to be coupled to a current supply, wherein the voltage terminal and the current terminal are configured to be coupled to an input node of a device under test (DUT) field effect transistor (FET) mounted on a wafer through probe needles; 
 an overlap resistor capacitor (RC) element coupled to an electrically neutral node and to the input node of the DUT FET, the overlap RC element being configured to inject overlap current into the input node of the DUT FET in response to the DUT FET transitioning from a cutoff region to a linear region, and the current supply is configured to inject a current into the input node of the DUT FET in response to depletion of the overlap current during an interval of time that the DUT FET is operating in the linear region; 
 an analog to digital (ADC) voltage capture module configured to capture a voltage between an input node and an output node of the DUT FET; 
 a resistive element configured to be coupled to the output node of the DUT FET and to an electrically neutral node through the probe needles; 
 an ADC current capture module coupled in parallel to the resistive element configured to measure a current across the resistive element; and 
 a driver configured to be coupled to a gate of the DUT FET through the probe needles, wherein the probe card is configured to repeatedly switch the DUT FET from a cutoff region to a linear region while a voltage and current is applied to the input node of the DUT FET. 
 
     
     
       13. The probe card of  claim 12 , wherein the DUT is a gallium nitride (GaN) FET. 
     
     
       14. The probe card of  claim 13 , wherein the ADC voltage capture module is configured to capture at least 20 million voltage measurements per second and the ADC current capture module is configured to capture at least 20 million current measurements per second. 
     
     
       15. The probe card of  claim 14 , wherein the ADC voltage capture module and the ADC current capture module are configured to provide data to a data acquisition system of an automatic test equipment to measure a drain to source on resistance of the GaN FET. 
     
     
       16. The probe card of  claim 12 , wherein the voltage supply supplies a voltage of at least 1 kilovolt (kV) and the overlap RC element is charged by the voltage supply in response to the DUT FET operating in the cutoff region. 
     
     
       17. A method for testing a device under test (DUT), the method comprising:
 coupling probe needles extending from a probe card to an input port, an output port and a gate of a DUT field effect transistor (FET), wherein the DUT FET is embedded in a wafer; 
 applying a direct current (DC) voltage to an input node of the DUT FET and to an overlap resistor capacitor (RC) element to charge the RC element; 
 switching the DUT FET between a cutoff region and a linear region by applying a time varying signal to a gate of the DUT FET, wherein current is injected into the input node of the DUT FET from the overlap RC element and voltage is applied to the input node of the DUT FET during time intervals that the DUT FET switches from the cutoff region to the linear region; 
 injecting a DC current to the input node of the DUT FET in response to depletion of the current injected by the overlap RC element during an interval of time the DUT FET is operating in the linear region; 
 measuring, by an analog to digital (ADC) voltage capture module of the probe card, a voltage between an input node and an output node of the DUT FET during the switching of the DUT FET; and 
 measuring, by an ADC current capture module of the probe card, coupled in parallel to a resistive element coupled to the output node of the DUT FET and an electrically neutral node, a current through the resistive element during the switching of the DUT FET. 
 
     
     
       18. The method of  claim 17 , further comprising:
 repeating the switching of the DUT FET at least fifty times; and 
 determining whether a drain to source on resistance of the DUT FET exceeds a threshold for one or more of the switches of the DUT FET. 
 
     
     
       19. The method of  claim 17 , further comprising:
 repeating the switching of the DUT FET at least fifty times; and 
 determining whether a drain to source on resistance of the DUT FET increases as a function of a number of switches at a rate that exceeds a threshold. 
 
     
     
       20. The method of  claim 17 , wherein the DUT is a gallium nitride (GaN) FET.