Synchronization of a clock generator divider setting and multiple independent component clock divider settings

Abstract

A device includes a clock generator configured to generate a root clock signal based on an input clock signal and a clock generator divider integer setting. The device also includes a first component coupled to the clock generator and configured to generate a first component clock signal based on the root clock signal and a first component divider integer setting. The device also includes a second component coupled to the clock generator and configured to generate a second component clock signal based on the root clock signal and a second component divider integer setting. The device also includes sync circuitry coupled to each of the clock generator, the first component, and the second component, wherein the sync circuitry is configured to perform synchronized adjustments to the root clock signal, the first component clock signal, and the second component clock signal.

The invention claimed is: 
     
       1. A device comprising:
 a synchronization circuit including a component divider setting input, a master clock divider setting input, a synchronization input, a first synchronization output, and a second synchronization output; and 
 a divider circuit including:
 a first latch coupled to the first synchronization output and a master clock output, wherein the first latch includes a first latch output; 
 a second latch coupled to the second synchronization output and the master clock output, wherein the second latch includes a second latch output; 
 a combiner circuit coupled to the first latch output and the second latch output, wherein the combiner circuit includes a combiner circuit output; 
 a clock gate controller coupled to the combiner circuit output, the second latch output, and the master clock output, wherein the clock gate controller includes a clock enable output; and 
 a clock gate coupled to the clock enable output and the master clock output. 
 
 
     
     
       2. The device of  claim 1 , wherein the synchronization circuit includes a first AND gate and a second AND gate. 
     
     
       3. The device of  claim 2 ,
 wherein the first AND gate is coupled to the component divider setting input and the synchronization input, and 
 wherein the first AND gate is coupled to the first synchronization output. 
 
     
     
       4. The device of  claim 2 ,
 wherein the second AND gate is coupled to the master clock divider setting input and the synchronization input, and 
 wherein the first AND gate is coupled to the second synchronization output. 
 
     
     
       5. The device of  claim 2 ,
 wherein the first AND gate includes an input, and 
 wherein the second AND gate includes an input coupled to the input of the first AND gate. 
 
     
     
       6. The device of  claim 1 , wherein the clock gate controller includes a multiplexer including:
 a first input coupled to the combiner circuit output; 
 a second input coupled to the second latch output; 
 a multiplexer control input; and 
 a multiplexer output. 
 
     
     
       7. The device of  claim 6 , wherein the clock gate controller includes an accumulator including:
 a first accumulator output; 
 a second accumulator output; 
 a first input coupled to the multiplexer output; and 
 a second input coupled to the master clock output. 
 
     
     
       8. The device of  claim 7 ,
 wherein the clock gate controller includes a third latch coupled to the first accumulator output and the master clock output, 
 wherein the accumulator includes a third input, and 
 wherein the third latch including a third latch output coupled to the third input of the accumulator. 
 
     
     
       9. The device of  claim 8 , wherein the third latch output is coupled to:
 the third input of the accumulator; and 
 the multiplexer control input. 
 
     
     
       10. The device of  claim 7 , wherein the second accumulator output is coupled to the clock enable output of the clock gate controller. 
     
     
       11. A system comprising:
 a first synchronization circuit including a synchronization control output; 
 a divider circuit including:
 a divider control input coupled to the synchronization control output; 
 a master clock divider setting input; and 
 a master clock output; 
 
 a first logic gate coupled to the synchronization control output, wherein the first logic gate includes a first synchronization output; 
 a second logic gate coupled to the synchronization control output and the master clock divider setting input, wherein the second logic gate includes a second synchronization output; 
 a first latch coupled to the first synchronization output and the master clock output, wherein the first latch includes a first latch output; 
 a second latch coupled to the second synchronization output and the master clock output, wherein the second latch includes a second latch output; 
 a combiner circuit coupled to the first latch output and the second latch output, wherein the combiner circuit includes a combiner circuit output; 
 a clock gate controller coupled to the combiner circuit output, the second latch output, and the master clock output, wherein the clock gate controller includes a clock enable output; and 
 a clock gate coupled to the clock enable output and the master clock output. 
 
     
     
       12. The system of  claim 11 , wherein the first logic gate is coupled to a component divider setting input. 
     
     
       13. The system of  claim 11 , wherein the clock gate controller includes a multiplexer including:
 a first input coupled to the combiner circuit output; 
 a second input coupled to the second latch output; 
 a multiplexer control input; and 
 a multiplexer output. 
 
     
     
       14. The system of  claim 13 , wherein the clock gate controller includes an accumulator including:
 a first accumulator output; 
 a second accumulator output; 
 a first input coupled to the multiplexer output; and 
 a second input coupled to the master clock output. 
 
     
     
       15. The system of  claim 14 ,
 wherein the clock gate controller includes a third latch coupled to the first accumulator output and the master clock output, 
 wherein the accumulator includes a third input, and 
 wherein the third latch including a third latch output coupled to the third input of the accumulator. 
 
     
     
       16. The system of  claim 15 , wherein the third latch output is coupled to:
 the third input of the accumulator; and 
 the multiplexer control input. 
 
     
     
       17. The system of  claim 14 , wherein the second accumulator output is coupled to the clock enable output of the clock gate controller. 
     
     
       18. A device comprising:
 a first logic gate coupled to a component divider setting input and a synchronization input, wherein the first logic gate includes a first synchronization output; 
 a second logic gate coupled to a master clock divider setting input and the synchronization input, wherein the second logic gate includes a second synchronization output; 
 a first latch coupled to the first synchronization output and a master clock output, wherein the first latch includes a first latch output; 
 a second latch coupled to the second synchronization output and the master clock output, wherein the second latch includes a second latch output; 
 a combiner circuit coupled to the first latch output and the second latch output, wherein the combiner circuit includes a combiner circuit output; 
 a multiplexer including:
 inputs coupled to the combiner circuit output and to the second latch output; 
 a multiplexer control input; and 
 a multiplexer output; 
 
 an accumulator including:
 a first accumulator output; 
 a second accumulator output; 
 a first input coupled to the multiplexer output; and 
 a second input coupled to the master clock output; and 
 
 a clock gate coupled to the first accumulator output and the master clock output. 
 
     
     
       19. The device of  claim 18 , further comprising a third latch coupled to the second accumulator output and the master clock output,
 wherein the accumulator includes a third input, and 
 wherein the third latch including a third latch output coupled to the third input of the accumulator. 
 
     
     
       20. The device of  claim 19 , wherein the third latch output is coupled to:
 the third input of the accumulator; and 
 the multiplexer control input.