Memory page manager

Abstract

Techniques are disclosed relating to managing page pools for sets of processing work. In some embodiments, a processor assigns sets of processing work to respective primary slots. Page manager circuitry may maintain, in a memory, page pool descriptor information for memory pages allocated to multiple different page pools, maintain a mapping of multiple primary slots of the processor circuitry to a first page pool of the page pools, and cache page pool descriptor entries in the page pool descriptor cache. The page manager circuitry may provide pages to requesting client circuitry from the first page pool for the multiple mapped primary slots. In some embodiments, the page manager circuitry pre-fetches virtual pages. The page manager circuitry may include primary and distribute components.

What is claimed is: 
     
       1. An apparatus, comprising:
 processor circuitry configured to assign sets of processing work to respective primary slots; 
 a page pool descriptor cache; and 
 page manager circuitry configured to:
 maintain, in memory circuitry, page pool descriptor information that indicates memory pages allocated to multiple different page pools; 
 maintain a mapping of multiple primary slots of the processor circuitry to a first page pool of the page pools; 
 cache page pool descriptor information from the memory circuitry in the page pool descriptor cache, wherein the page pool descriptor cache includes multiple entry circuits and a given entry circuit is configured to store the following information for a cached page pool descriptor:
 a base address for the pool; and 
 page pool size information; and 
 
 provide pages to requesting client circuitry from the first page pool for the multiple mapped primary slots. 
 
 
     
     
       2. The apparatus of  claim 1 , wherein the page manager circuitry includes a prefetch queue configured to store prefetched pages for one or more primary slots from one or more corresponding page pools. 
     
     
       3. The apparatus of  claim 1 , wherein the page pools provide pages for a page table hierarchy controlled by a memory management unit (MMU) of the processor circuitry, wherein the MMU uses the page table hierarchy to translate graphics space addresses to virtual addresses. 
     
     
       4. The apparatus of  claim 1 , wherein the page manager circuitry is configured to:
 receive a page reservation request for a set of processing work; and 
 reserve a requested number of pages in response to determining that a corresponding page pool includes a sufficient number of pages for the request; 
 wherein the apparatus is configured to launch the set of processing work only after reservation of the requested number of pages by the page manager circuitry. 
 
     
     
       5. The apparatus of  claim 1 , wherein the page manager circuitry includes:
 primary page manager circuitry; and 
 multiple distributed page manager circuits configured to interface with memory management units for different processor sub-units. 
 
     
     
       6. The apparatus of  claim 5 , wherein the primary page manager circuitry is configured to maintain a mapping of a given primary slot to a set of one or more distributed slots. 
     
     
       7. The apparatus of  claim 6 , wherein the primary page manager circuitry includes storage for prefetched pages from respective page pools;
 wherein the distributed page manager circuits include storage for prefetched pages from respective page pools; and 
 wherein the primary page manager circuitry is configured to begin distributing prefetched pages to the distributed page manager circuits in response to the given primary slot starting execution and completion of the mapping of the given primary slot to the set of one or more distributed slots. 
 
     
     
       8. The apparatus of  claim 7 , wherein the primary page manager circuitry is configured to distribute prefetched pages to distributed page manager circuits according to a credit mechanism and the distributed page manager circuits are configured to distribute pages to memory management units according to a credit mechanism. 
     
     
       9. The apparatus of  claim 1 , wherein the apparatus is a mobile computing device that includes:
 a central processing unit; 
 a graphic processing unit; 
 a display; and 
 network interface circuitry. 
 
     
     
       10. The apparatus of  claim 1 , wherein the apparatus is a graphics processing unit and the sets of processing work are sets of graphics processing work. 
     
     
       11. A method, comprising:
 assigning, by processor circuitry, sets of processing work to respective primary slots; 
 maintaining, in memory by page manager circuitry, page pool descriptor information that indicates memory pages allocated to multiple different page pools; 
 maintaining, by the page manager circuitry, a mapping of multiple primary slots of the processor circuitry to a first page pool of the page pools;
 caching, by the page manager circuitry using a page pool descriptor cache, cache page pool descriptor information from the memory in the page pool descriptor cache, wherein the page pool descriptor cache includes multiple entry circuits and a given entry circuit is configured stores the following information for a cached page pool descriptor:
 a base address for the pool; and 
 page pool size information; and 
 
 
 providing, by the page manager circuitry, pages to requesting client circuitry from the first page pool for the multiple mapped primary slots. 
 
     
     
       12. The method of  claim 11 , further comprising:
 prefetching and storing, by the page manager circuitry, pages for one or more primary slots in a prefetch queue from one or more corresponding page pools. 
 
     
     
       13. The method of  claim 11 , further comprising:
 receiving, by the page manager circuitry, a page reservation request for a set of processing work; 
 reserving, by the page manager circuitry, a requested number of pages in response to determining that a corresponding page pool includes a sufficient number of pages for the request; and 
 waiting, by the processor circuitry, to launch the set of processing work until reservation of the requested number of pages by the page manager circuitry. 
 
     
     
       14. The method of  claim 11 , further comprising:
 maintaining, by the page manager circuitry, a mapping of primary slots to distributed slots; 
 queueing prefetched pages in a primary prefetch queue; 
 distributing pages from the primary prefetch queue to multiple distributed prefetch queues; and 
 distributed pages from at least one distributed prefetch queue to a cache for a page table hierarchy for translating graphics space addresses to virtual addresses. 
 
     
     
       15. A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, wherein the design information specifies that the circuit includes:
 processor circuitry configured to assign sets of processing work to respective primary slots; 
 a page pool descriptor cache; and 
 page manager circuitry configured to:
 maintain, in memory circuitry, page pool descriptor information that indicates memory pages allocated to multiple different page pools; 
 maintain a mapping of multiple primary slots of the processor circuitry to a first page pool of the page pools; 
 cache page pool descriptor information from the memory circuitry in the page pool descriptor cache, wherein the page pool descriptor cache includes multiple entry circuits and a given entry circuit is configured to store the following information for a cached page pool descriptor:
 a base address for the pool; and 
 page pool size information; and 
 
 provide pages to requesting client circuitry from the first page pool for the multiple mapped primary slots. 
 
 
     
     
       16. The non-transitory computer readable storage medium of  claim 15 , wherein the page manager circuitry includes a prefetch queue configured to store prefetched pages for one or more primary slots from one or more corresponding page pools. 
     
     
       17. The non-transitory computer readable storage medium of  claim 15 , wherein the page manager circuitry is configured to:
 receive a page reservation request for a set of processing work; and 
 reserve a requested number of pages in response to determining that a corresponding page pool includes a sufficient number of pages for the request; 
 wherein the circuit is configured to launch the set of processing work only after reservation of the requested number of pages by the page manager circuitry. 
 
     
     
       18. The non-transitory computer readable storage medium of  claim 15 , wherein the page manager circuitry includes:
 primary page manager circuitry; and 
 multiple distributed page manager circuits configured to interface with memory management units for different processor sub-units. 
 
     
     
       19. The non-transitory computer readable storage medium of  claim 18 , wherein the primary page manager circuitry is configured to maintain a mapping of a given primary slot to a set of one or more distributed slots. 
     
     
       20. The non-transitory computer readable storage medium of  claim 19 , wherein the primary page manager circuitry includes storage for prefetched pages from respective page pools;
 wherein the distributed page manager circuits include storage for prefetched pages from respective page pools; and 
 wherein the primary page manager circuitry is configured to begin distributing prefetched pages to the distributed page manager circuits in response to the given primary slot starting execution and completion of the mapping of the given primary slot to the set of one or more distributed slots.