Multiprocessor system and data management method thereof

Abstract

A multiprocessor system includes a plurality of processors, a first cache device corresponding to a first processor of the plurality of processors and including a first cache memory configured to store a plurality of first cache lines, and a second cache device at different level than the first cache device, corresponding to the plurality of processors, and including a second cache memory that stores a plurality of second cache lines, in which the first cache device is configured to, in response to a request related to data access, search the first cache memory for data, and the second cache device is configured to, in response to the data cache-missed in the first cache memory, search the second cache memory for data, and in response to the data cache-hit in the second cache memory, set cache line of the second cache memory corresponding to the data as clean cache line.

What is claimed is: 
     
       1. A multiprocessor system comprising:
 a plurality of processors: 
 a first cache device corresponding to a first processor of the plurality of processors, and including a first cache memory configured to store a plurality of first cache lines; and 
 a second cache device at a lower level than the first cache device, corresponding to the plurality of processors, and including a second cache memory configured to store a plurality of second cache lines, 
 wherein the second cache device is configured to:
 in response to a first request related to accessing predetermined data, search the second cache memory for the data; and 
 in response to the data being cache-missed in the second cache memory, read the data from a cache memory at a lower level than the second cache device or from a main memory, allocate any one of the plurality of second cache lines of the second cache memory and store the data, and set a cache line corresponding to the data, of the plurality of second cache lines, as a dirty cache line, 
 
 the first cache device is configured to:
 after the first request, search the first cache memory for the data in response to a second request related to accessing the data, 
 
 the second cache device is configured to:
 in response to the data being cache-missed in the first cache memory, search the second cache memory for the data; and 
 in response to the cache-missed data in the first cache memory being cache-hit in the second cache memory, change the cache line corresponding to the data of the plurality of second cache lines of the second cache memory from the dirty cache line to a clean cache line, and 
 
 the first cache device is configured to:
 allocate any one of the plurality of first cache lines of the first cache memory and store the data, and set a cache line corresponding to the data, of the plurality of first cache lines, as a dirty cache line. 
 
 
     
     
       2. The multiprocessor system according to  claim 1 , wherein the first cache device is further configured to, according to a flush request for the first cache memory, change the allocated cache line of the first cache memory from the dirty cache line to a clean cache line. 
     
     
       3. The multiprocessor system according to  claim 1 , wherein the first cache device is further configured to, in response to the data being cache-missed in the first cache memory, according to AXI protocol, transmit, to the second cache device, a signal indicating that the data is cacheable in the first cache memory. 
     
     
       4. The multiprocessor system according to  claim 1 , wherein the second cache device is further configured to, in response to the data being cache-hit in the second cache memory, according to AXI protocol, transmit, to the first cache device, a signal indicating that the cache line of the second cache memory corresponding to the data is set as the clean cache line. 
     
     
       5. The multiprocessor system according to  claim 1 , wherein the first cache memory and the second cache memory are of write-back type. 
     
     
       6. The multiprocessor system according to  claim 1 , wherein the first cache memory is of read-allocate write-back type, and the second cache memory is of write-allocate write-back type. 
     
     
       7. A multiprocessor system comprising:
 a plurality of processors: 
 a first cache memory corresponding to each of the plurality of processors; 
 a first cache controller configured to read data from the first cache memory or write data to the first cache memory; 
 a second cache memory corresponding to the plurality of processors; and 
 a second cache controller configured to read data from the second cache memory or write data to the second cache memory, 
 wherein the second cache controller is configured to:
 in response to a first request related to accessing predetermined data, search the second cache memory for the data; and 
 in response to the data being cache-missed in the second cache memory, read the data from a cache memory at a lower level than the second cache memory or from a main memory, allocate any one of a plurality of second cache lines of the second cache memory and store the data, and set a cache line corresponding to the data, of the plurality of second cache lines, as a dirty cache line, 
 
 the first cache controller is configured to:
 after the first request, receive a second request related to accessing the data from a first processor of the plurality of processors; and 
 in response to the second request, search the first cache memory corresponding to the first processor for the data, 
 
 the second cache controller is configured to:
 in response to the data being cache-missed in the first cache memory, search the second cache memory for the data; and 
 in response to the cache-missed data in the first cache memory being cache-hit in the second cache memory, change the cache line corresponding to the data of the plurality of second cache lines of the second cache memory from the dirty cache line to a clean cache line, and 
 
 the first cache controller is configured to:
 allocate any one of a plurality of first cache lines of the first cache memory and store the data, and set a cache line corresponding to the data, of the plurality of first cache lines, as a dirty cache line. 
 
 
     
     
       8. A data management method of a system, wherein the system comprises: a plurality of processors; a first cache memory corresponding to a first processor of the plurality of processors, and a first cache controller; and a second cache memory at a different level from the first cache memory and corresponding to the plurality of processors, and a second cache controller, the method comprising:
 by the second cache controller, in response to a first request related to accessing predetermined data, searching the second cache memory for the data; 
 by the second cache controller, in response to the data being cache-missed in the second cache memory, reading the data from a cache memory at a lower level than the second cache memory or from a main memory, allocating any one of a plurality of second cache lines of the second cache memory and storing the data, and setting a cache line corresponding to the data, of the plurality of second cache lines, as a dirty cache line; 
 by the first cache controller, after the first request, according to a second request related to accessing the data generated by the first processor, searching the first cache memory for the data; 
 by the second cache controller, in response to the data being cache-missed in the first cache memory, searching the second cache memory for the data; 
 by the second cache controller, in response to the data cache-missed in the first cache memory being cache-hit in the second cache memory, changing the cache line corresponding to the data of the plurality of second cache lines of the second cache memory from the dirty cache line to a clean cache line; and 
 by the first cache controller, allocating any one of a plurality of first cache lines of the first cache memory and storing the data, and setting a cache line corresponding to the data, of the plurality of first cache lines, as a dirty cache line. 
 
     
     
       9. The method according to  claim 8 , further comprising, according to a flush request for the first cache memory, changing the allocated line of the first cache memory from the dirty cache line to a clean cache line. 
     
     
       10. The method according to  claim 8 , wherein the searching the second cache memory for the data includes in response to the data being cache-missed in the first cache memory, according to AXI protocol, receiving a signal indicating that the data is cacheable in the first cache memory. 
     
     
       11. The method according to  claim 8 , wherein the changing the cache line of the second cache memory from the dirty cache line to the clean cache line includes, in response to the data being cache-hit in the second cache memory, according to AXI protocol, transmitting a signal indicating that the cache line of the second cache memory corresponding to the data is set as the clean cache line.