Shared traffic manager

Abstract

A traffic manager is shared amongst two or more egress blocks of a network device, thereby allowing traffic management resources to be shared between the egress blocks. Schedulers within a traffic manager may generate and queue read instructions for reading buffered portions of data units that are ready to be sent to the egress blocks. The traffic manager may be configured to select a read instruction for a given buffer bank from the read instruction queues based on a scoring mechanism or other selection logic. To avoid sending too much data to an egress block during a given time slot, once a data unit portion has been read from the buffer, it may be temporarily stored in a shallow read data cache. Alternatively, a single, non-bank specific controller may determine all of the read instructions and write operations that should be executed in a given time slot.

What is claimed is: 
     
       1. A network switching apparatus comprising:
 a plurality of ingress ports configured to receive data units; 
 a plurality of egress ports configured to send the data units to other network devices; 
 a shared buffer memory in which the data units are stored, the shared buffer memory is shared among a plurality of egress queues; 
 a plurality of schedulers, each scheduler configured to schedule particular data units to be queued in a different set of one or more of the plurality of egress queues corresponding to a different set of one or more of the plurality of egress ports, each scheduler is associated with one or more read instruction queues among a plurality of read instruction queues, a scheduler generates a read instruction for reading a portion of a particular data unit from the shared buffer memory and places the read instruction in one of the one or more associated read instruction queues, the read instruction indicates a destination egress port that the portion of the particular data unit is to be sent and a location of the portion of the particular data unit in the shared buffer memory; 
 a traffic manager configured to determine an order in which to select read instructions from the plurality of read instruction queues, portions of data units associated with selected read instructions are placed in egress queues that correspond to the destination egress ports as indicated by the selected read instructions. 
 
     
     
       2. The network switching apparatus of  claim 1 ,
 wherein the shared buffer memory includes a plurality of banks, each bank limited to a particular number of operations in a given time slot; 
 wherein each scheduler of the plurality of schedulers is further configured to determine a given destination egress port to forward a given data unit toward; 
 wherein the traffic manager includes read operation selection logic configured to determine an order in which to read data units based on the plurality of read instruction queues, the data units being forwarded toward their corresponding destination egress ports after being read. 
 
     
     
       3. The network switching apparatus of  claim 1 ,
 wherein the traffic manager is further configured to determine priority scores for read instructions in the plurality of read instruction queues. 
 
     
     
       4. The network switching apparatus of  claim 1 ,
 wherein each of the read instruction queues is assigned to a bank of a plurality of banks in the shared buffer memory; 
 wherein the traffic manager includes read operation selection logic configured to, for at least each bank in the shared buffer memory that is not being written to during a given time slot, select a read instruction to execute within the bank during the given time slot from a set of read instruction queues associated with the bank. 
 
     
     
       5. The network switching apparatus of  claim 1 , wherein the shared buffer memory includes a plurality of banks, each of the banks is a set of single-ported memories across which data unit portions of the data units are striped, a given data unit destined for a given egress port being writeable to any of the banks that is not being read when the given data unit is received via an ingress port. 
     
     
       6. The network switching apparatus of  claim 1 , further comprising
 a plurality of ingress packet processors deployed between the ingress ports and the traffic manager, each coupled to a different set of one or more of the ingress ports, the ingress packet processors configured to process at least control portions of the data units before the data units are stored in the shared buffer memory; 
 a plurality of egress packet processors deployed between the traffic manager and the egress ports, each coupled to a different set of one or more of the egress ports, the egress packet processors configured to process at least control portions of the data units before the data units are forwarded to their corresponding destination egress ports. 
 
     
     
       7. The network switching apparatus of  claim 1 , further comprising:
 a plurality of ingress packet processors, each coupled to the traffic manager, and configured to process control portions of the data units before the data units are stored in the shared buffer memory; 
 a plurality of ingress arbiters, each coupled to one of the ingress packet processors and a different set of one or more of the ingress ports, the ingress arbiters configured to send control portions of the data units to the ingress packet processors and to store payload portions of the data units in the shared buffer memory. 
 
     
     
       8. The network switching apparatus of  claim 1 , wherein the traffic manager is a first traffic manager in the network switching apparatus, wherein the plurality of egress ports is a first plurality of egress ports, the network switching apparatus further comprising:
 a second plurality of egress ports; 
 a second traffic manager configured to forward second data units, also received via the plurality of ingress ports, to second destination egress ports in the second plurality of egress ports; 
 a crossbar coupled to the plurality of ingress ports, and directly connected to the first traffic manager and the second traffic manager. 
 
     
     
       9. A method comprising:
 receiving data units via a plurality of ingress ports; 
 storing the data units in a shared buffer memory, the shared buffer memory is shared among a plurality of egress queues; 
 scheduling, by a plurality of schedulers, particular data units to be queued in a different set of one or more of the plurality of egress queues corresponding to a different set of one or more of the plurality of egress ports, each scheduler is associated with one or more read instruction queues among a plurality of read instruction queues, a scheduler generates a read instruction for reading a portion of a particular data unit from the shared buffer memory and places the read instruction in one of the one or more associated read instruction queues, the read instruction indicates a destination egress port that the portion of the particular data unit is to be sent and a location of the portion of the particular data unit in the shared buffer memory; 
 determining an order in which to select read instructions from the plurality of read instruction queues; 
 placing portions of data units associated with selected read instructions in egress queues that correspond to the destination egress ports as indicated by the selected read instructions. 
 
     
     
       10. The method of  claim 9 ,
 wherein the shared buffer memory includes a plurality of banks, each bank limited to a particular number of operations in a given time slot; 
 wherein each scheduler of the plurality of schedulers is further configured to determine a given destination egress port to forward a given data unit toward; 
 wherein the traffic manager includes read operation selection logic configured to determine an order in which to read data units based on the plurality of read instruction queues, the data units being forwarded toward their corresponding destination egress ports after being read. 
 
     
     
       11. The method of  claim 9 , further comprising:
 determining priority scores for read instructions in the read instruction queues. 
 
     
     
       12. The method of  claim 9 , further comprising:
 wherein each of the read instruction queues is assigned to a bank of a plurality of banks in the shared buffer memory; 
 for at least each bank in the shared buffer memory that is not being written to during a given time slot, selecting a read instruction to execute within the bank during the given time slot from the set of read instruction queues associated with the bank. 
 
     
     
       13. The method of  claim 9 , wherein the shared buffer memory includes a plurality of banks, each of the banks is a set of single-ported memories across which data unit portions of the data units are striped, a given data unit destined for a given egress port being writeable to any of the banks that is not being read when the given data unit is received via an ingress port. 
     
     
       14. The method of  claim 9 , further comprising:
 wherein a plurality of ingress packet processors, each ingress packet processor coupled to a different set of one or more of the ingress ports; 
 wherein a plurality of egress packet processors, each egress packet processor coupled to a different set of one or more of the egress ports; 
 processing, by the ingress packet processors, at least control portions of the data units before the data units are stored in the shared buffer memory; 
 processing, by the egress packet processors, at least control portions of the data units before the data units are sent to their corresponding destination egress ports. 
 
     
     
       15. The method of  claim 9 , further comprising:
 wherein a plurality of ingress packet processors, each ingress packet processor coupled to a different set of one or more of the ingress ports; 
 wherein a plurality of ingress arbiters are each coupled to one of the ingress packet processors and a different set of one or more of the ingress ports; 
 processing control portions of the data units before the data units are stored in the shared buffer memory; 
 sending control portions of the data units from the ingress arbiters to the ingress packet processors; 
 storing payload portions of the data units in the shared buffer memory. 
 
     
     
       16. The method of  claim 9 , further comprising:
 wherein the plurality of egress ports is a first plurality of egress ports; 
 via a crossbar deployed between the ingress ports, receiving the data units from the first plurality of egress ports and second data units from a second plurality of egress ports; 
 forwarding the second data units toward second destination egress ports in a second plurality of egress ports. 
 
     
     
       17. One or more non-transitory computer-readable medium storing instructions that, when executed by one or more computing devices, cause:
 receiving data units via a plurality of ingress ports; 
 storing the data units in a shared buffer memory, the shared buffer memory is shared among a plurality of egress queues; 
 scheduling, by a plurality of schedulers, particular data units to be queued in a different set of one or more of the plurality of egress queues corresponding to a different set of one or more of the plurality of egress ports, each scheduler is associated with one or more read instruction queues among a plurality of read instruction queues, a scheduler generates a read instruction for reading a portion of a particular data unit from the shared buffer memory and places the read instruction in one of the one or more associated read instruction queues, the read instruction indicates a destination egress port that the portion of the particular data unit is to be sent and a location of the portion of the particular data unit in the shared buffer memory; 
 determining an order in which to select read instructions from the plurality of read instruction queues; 
 placing portions of data units associated with selected read instructions in egress queues that correspond to the destination egress ports as indicated by the selected read instructions. 
 
     
     
       18. The one or more non-transitory computer-readable medium of  claim 17 ,
 wherein the shared buffer memory includes a plurality of banks, each bank limited to a particular number of operations in a given time slot; 
 wherein each scheduler of the plurality of schedulers is further configured to determine a given destination egress port to forward a given data unit toward; 
 wherein the traffic manager includes read operation selection logic configured to determine an order in which to read data units based on the plurality of read instruction queues, the data units being forwarded toward their corresponding destination egress ports after being read. 
 
     
     
       19. The one or more non-transitory computer-readable medium of  claim 17 , wherein the instructions that, when executed by the one or more computing devices, further cause:
 determining priority scores for read instructions in the read instruction queues. 
 
     
     
       20. The one or more non-transitory computer-readable medium of  claim 17 , wherein the instructions that, when executed by the one or more computing devices, further cause:
 wherein each of the read instruction queues is assigned to a bank of a plurality of banks in the shared buffer memory; 
 for at least each bank in the shared buffer memory that is not being written to during a given time slot, selecting a read instruction to execute within the bank during the given time slot from the set of read instruction queues associated with the bank.