Vertical semiconductor memory device having stacked shifted axis channels

Abstract

According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers.

What is claimed is: 
     
       1. A semiconductor memory device, comprising:
 a source layer; 
 a first unit provided above the source layer, the first unit including at least a source-side selection gate layer; 
 a second unit stacked above the first unit, the second unit including a plurality of first electrode layers as control gates of memory cells, the first electrode layers being alternately stacked in a stacking direction with a plurality of first insulating layers therebetween; 
 a bit line provided above the second unit; 
 a first columnar part piercing the first unit in the stacking direction, the first columnar part including a first channel body with a tubular configuration and a first core insulator part provided inside the first channel body with the tubular configuration; and 
 a second columnar part piercing the second unit in the stacking direction, the second columnar part including a second channel body with a tubular configuration and a second core insulator part provided inside the second channel body with the tubular configuration, wherein 
 the first channel body and the second channel body are formed as one body and are connected with each other in the stacking direction, and 
 a central axis of the first columnar part piercing the first unit is shifted in a direction perpendicular to the stacking direction from a central axis of the second columnar part piercing the second unit. 
 
     
     
       2. The device according to  claim 1 , wherein
 the first channel body and the second channel body are electrically connected between the source layer and the bit line. 
 
     
     
       3. The device according to  claim 1 , wherein
 a stepped portion is formed between a side wall of the first columnar part and a side wall of the second columnar part. 
 
     
     
       4. The device according to  claim 3 , wherein
 the source-side selection gate layer is provided around the side wall of the first columnar part and the first electrode layers are provided around the side wall of the second columnar part. 
 
     
     
       5. The device according to  claim 1 , wherein
 the first core insulator part and the second core insulator part are formed as one body. 
 
     
     
       6. The device according to  claim 1 , wherein
 the first electrode layers include silicon and the first insulating layers include silicon oxide. 
 
     
     
       7. The device according to  claim 1 , wherein the first and second core insulator parts include silicon oxide. 
     
     
       8. The device according to  claim 1 , further comprising:
 a second insulating layer provided above the first unit and below the second unit. 
 
     
     
       9. The device according to  claim 8 , wherein
 the second insulating layer includes a material same as the first insulating layers. 
 
     
     
       10. The device according to  claim 8 , wherein
 the second insulating layer includes silicon oxide. 
 
     
     
       11. A semiconductor memory device, comprising:
 a source layer; 
 a first unit provided above the source layer, the first unit including at least a source-side selection gate layer; 
 a second unit stacked above the first unit, the second unit including a plurality of first electrode layers as control gates of memory cells, the first electrode layers being alternately stacked in a stacking direction with a plurality of first insulating layers therebetween; 
 a bit line provided above the second unit; 
 a first columnar part piercing the first unit in the stacking direction; and 
 a second columnar part piercing the second unit in the stacking direction, wherein 
 the first columnar part includes a first channel body portion with a tubular configuration at least on a side of the second columnar part and the second columnar part includes a second channel body portion with a tubular configuration at least on a side of the first columnar part, 
 a core insulator part is integrally formed inside the first channel body portion with the tubular configuration and inside the second channel body portion with the tubular configuration, and 
 a central axis of the first columnar part piercing the first unit is shifted in a direction perpendicular to the stacking direction from a central axis of the second columnar part piercing the second unit. 
 
     
     
       12. The device according to  claim 11 , wherein
 the first channel body portion and the second channel body portion are formed as one body. 
 
     
     
       13. The device according to  claim 11 , wherein
 the first channel body portion and the second channel body portion are electrically connected between the source layer and the bit line. 
 
     
     
       14. The device according to  claim 11 , wherein
 a stepped portion is formed between a side wall of the first columnar part and a side wall of the second columnar part. 
 
     
     
       15. The device according to  claim 14 , wherein
 the source-side selection gate layer is provided around the side wall of the first columnar part and the first electrode layers are provided around the side wall of the second columnar part. 
 
     
     
       16. The device according to  claim 11 , wherein
 the first electrode layers include silicon and the first insulating layers include silicon oxide. 
 
     
     
       17. The device according to  claim 11 , wherein the core insulator part includes silicon oxide. 
     
     
       18. The device according to  claim 11 , further comprising:
 a second insulating layer provided above the first unit and below the second unit. 
 
     
     
       19. The device according to  claim 18 , wherein
 the second insulating layer includes a material same as the first insulating layers. 
 
     
     
       20. The device according to  claim 18 , wherein
 the second insulating layer includes silicon oxide.