Circuitry and methods for mitigating imbalance in image sensors with multiple readout paths

Abstract

An image sensor may include a pixel array and associated readout paths calibration circuitry. The image sensor may include first column readout circuits formed along a first edge of the pixel array and second column readout circuits formed along a second opposing edge of the pixel array. The readout paths calibration circuitry may include one or more first calibration readout circuits located by the first edge of the array, one or more second calibration readout circuits located by the second edge of the array, and an error detection circuit configured to output an error signal based on signals output from the one or more first calibration readout circuits and the one or more second calibration readout circuits. The one or more second calibration readout circuits and the second column readout circuits can receive a reference voltage that is dynamically adjusted based on the error signal.

What is claimed is: 
     
       1. An image sensor comprising:
 a pixel array; 
 first readout circuits disposed at a first location relative to the pixel array and configured to receive signals from the pixel array; 
 second readout circuits disposed at a second location, different than the first location, relative to the pixel array and configured to receive signals from the pixel array; 
 a first calibration readout circuit disposed by the first readout circuits and configured to receive a calibration voltage; 
 a second calibration readout circuit disposed by the second readout circuits and configured to receive the calibration voltage; and 
 an error detection circuit configured to output an error signal based on signals output from the first and second calibration readout circuits. 
 
     
     
       2. The image sensor of  claim 1 , wherein the first readout circuits are disposed along a first edge of the pixel array and wherein the second readout circuits are disposed along a second edge of the pixel array different than the first edge, further comprising:
 a calibration voltage generator configured to output the calibration voltage onto a column line that is coupled to the first and second calibration readout circuits. 
 
     
     
       3. The image sensor of  claim 2 , wherein the calibration voltage generator is disposed at a midpoint of the column line between the first and second calibration readout circuits. 
     
     
       4. The image sensor of  claim 1 , further comprising:
 one or more black pixels configured to output the calibration voltage onto a column line that is coupled to the first and second calibration readout circuits. 
 
     
     
       5. The image sensor of  claim 1 , wherein the first calibration readout circuit comprises a first analog-to-digital converter and wherein the second calibration readout circuit comprises a second analog-to-digital converter. 
     
     
       6. The image sensor of  claim 1 , further comprising:
 a first reference voltage generator configured to output a first reference voltage to the first calibration readout circuit and to the first readout circuits. 
 
     
     
       7. The image sensor of  claim 6 , further comprising:
 a second reference voltage generator configured to output a second reference voltage to the second calibration readout circuit and to the second readout circuits. 
 
     
     
       8. The image sensor of  claim 7 , further comprising:
 a loop filter coupled between the error detection circuit and the second reference voltage generator. 
 
     
     
       9. The image sensor of  claim 8 , further comprising:
 a reference voltage controller coupled between the loop filter and the second reference voltage generator. 
 
     
     
       10. The image sensor of  claim 1 , further comprising:
 at least one additional calibration readout circuit disposed by the first calibration readout circuit and configured to receive the calibration voltage; and 
 an averaging circuit configured to receive signals from the first calibration readout circuit and the at least one additional calibration readout circuit, wherein the averaging circuit is coupled between the first calibration readout circuit and the error detection circuit. 
 
     
     
       11. The image sensor of  claim 1 , further comprising:
 at least one additional calibration readout circuit disposed by the second calibration readout circuit and configured to receive the calibration voltage; and 
 an averaging circuit configured to receive signals from the second calibration readout circuit and the at least one additional calibration readout circuit, wherein the averaging circuit is coupled between the second calibration readout circuit and the error detection circuit. 
 
     
     
       12. Imaging circuitry comprising:
 a pixel array; 
 first readout circuits disposed along a first side of the pixel array; 
 second readout circuits disposed along a second side, different than the first side, of the pixel array; 
 a calibration voltage generator disposed by the first readout circuits and configured to generate a calibration voltage; 
 one or more first calibration readout circuits configured to receive the calibration voltage; 
 one or more second calibration readout circuits configured to receive the calibration voltage via a first column line; and 
 one or more third calibration readout circuits configured to receive the calibration voltage via the first column line and a second column line separate from the first column line. 
 
     
     
       13. The imaging circuitry of  claim 12 , further comprising:
 an error detection circuit configured to output an error signal based on signals output from the one or more first calibration readout circuits, the one or more second calibration readout circuits, and the one or more third calibration readout circuits. 
 
     
     
       14. The imaging circuitry of  claim 13 , further comprising:
 an averaging circuit coupled between the one or more second calibration readout circuits and the error detection circuit. 
 
     
     
       15. The imaging circuitry of  claim 13 , further comprising:
 a first averaging circuit coupled between the one or more first calibration readout circuits and the error detection circuit; and 
 a second averaging circuit coupled between the one or more third calibration readout circuits and the error detection circuit. 
 
     
     
       16. The imaging circuitry of  claim 15 , further comprising:
 a weighting circuit configured to receive a first average value from the first averaging circuit, to receive a second average value from the second averaging circuit, and to output a weighted value based on the first and second average values to the error detection circuit. 
 
     
     
       17. The imaging circuitry of  claim 13 , further comprising:
 a first reference voltage generator configured to output a first reference voltage to the one or more first calibration readout circuits and to the first readout circuits. 
 
     
     
       18. The imaging circuitry of  claim 17 , further comprising:
 a second reference voltage generator configured to output a second reference voltage to the one or more second calibration readout circuits and to the second readout circuits. 
 
     
     
       19. The image sensor of  claim 18 , further comprising:
 a loop filter configured to filter the error signal; and 
 a reference voltage controller coupled between the loop filter and the second reference voltage generator. 
 
     
     
       20. A method of operating imaging circuitry comprising:
 with a pixel array, capturing an image; 
 with first column readout circuits formed along a first peripheral edge of the pixel array, reading signals out from the pixel array via a first readout path; 
 with second column readout circuits formed along a second peripheral edge of the pixel array, reading signals out from the pixel array via a second readout path; 
 generating two or more calibration voltages to characterize the first readout path using a first equation having one or more first coefficients and to characterize the second readout path using a second equation having one or more second coefficients; 
 supplying a first reference voltage to the first column readout circuits; 
 supplying a second reference voltage to the second column readout circuits; and 
 adjusting the first and second reference voltages to match the one or more first coefficients with the one or more second coefficients.