Method of performing internal processing operations with pre-defined protocol interface of memory device

Abstract

A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.

What is claimed is: 
     
       1. A memory device comprising:
 a memory cell array including a first memory region and a second memory region; 
 a processing-in-memory (PIM) engine configured to perform an internal processing operation on the first memory region; 
 a mode selector circuit configured to activate a processing mode selection signal for controlling the memory device to enter an internal processing mode when first addresses are received sequentially along with sequential write commands and when bit values of the first addresses match bit values of a first back-to-back address sequence of a PIM mode entering code associated with the sequential write commands, the PIM mode entering code being stored in the mode selector circuit; and 
 a command converter circuit configured to convert a received command into a PIM command to perform the internal processing operation in response to the activation of the processing mode selection signal. 
 
     
     
       2. The memory device of  claim 1 , wherein the mode selector circuit is further configured to receive the first addresses sequentially and compare the PIM mode entering code with the first addresses to determine whether the bit values of the first addresses match the bit values of the first back-to-back address sequence of the PIM mode entering code. 
     
     
       3. The memory device of  claim 1 , wherein the command converter circuit is further configured convert a read command into an internal processing read command, and the PIM engine is further configured to read internal processing data from memory cells of the first memory region in response to the internal processing read command and perform the internal processing operation by using the read internal processing data. 
     
     
       4. The memory device of  claim 1 , wherein the command converter circuit is further configured to convert a write command into an internal processing write command, and the PIM engine is further configured to write internal processing data obtained as a processing result of performing the internal processing operation, to memory cells of the first memory region, in response to the internal processing write command. 
     
     
       5. The memory device of  claim 1 , wherein the mode selector circuit is further configured to store a PIM mode exiting code and deactivate the processing mode selection signal for controlling the memory device to exit the internal processing operation based on the PIM mode exiting code, and the PIM mode exiting code includes a second back-to-back address sequence associated with the sequential write commands. 
     
     
       6. The memory device of  claim 5 , wherein the mode selector circuit is further configured to receive second addresses sequentially, compare the PIM mode exiting code with the second addresses, and deactivate the processing mode selection signal when the sequential second addresses match second back-to-back address sequence of the PIM mode exiting code associated with the sequential write commands. 
     
     
       7. The memory device of  claim 5 , wherein the memory device enters a normal mode in response to the deactivation of the processing mode selection signal. 
     
     
       8. The memory device of  claim 1 , wherein the memory device supports a double data rate (DDR) protocol or a low power double data rate (LPDDR) protocol. 
     
     
       9. A method of operating a memory device including a memory cell array, the memory cell array including a first memory region and a second memory region, and a processing-in-memory (PIM) engine performing an internal processing operation, the method comprising:
 activating a processing mode selection signal for controlling the memory device to enter an internal processing mode operation when first addresses are received sequentially along with sequential writes commands and when bit values of the first addresses match bit values of a first back-to-back address sequence of a PIM mode entering code associated with the sequential write commands, the PIM mode entering code being stored in the memory device; 
 converting a received command into an internal processing command in response to the activation of the processing mode selection signal; and 
 performing, by the PIM engine, the internal processing operation on the first memory region in response to the internal processing command. 
 
     
     
       10. The method of  claim 9 , further comprising:
 receiving the first addresses sequentially; and 
 comparing the back-to-back address sequence of the PIM mode entering code with the first addresses to determine whether the bit values of the first addresses match the bit values of PIM mode entering code. 
 
     
     
       11. The method of  claim 9 , further comprising:
 receiving a read command; 
 converting the read command into an internal processing read command; 
 reading internal processing data from memory cells of the first memory region in response to the internal processing read command; and 
 performing, by the PIM engine, the internal processing operation by using the read internal processing data. 
 
     
     
       12. The method of  claim 9 , further comprising:
 receiving a write command; converting the write command into an internal processing write command; and 
 writing internal processing data obtained as a processing result of the performing of the internal processing operation, to memory cells of the first memory region, in response to the internal processing write command. 
 
     
     
       13. The method of  claim 9 , further comprising deactivating the processing mode selection signal for controlling the memory device to exit the internal processing operation based on a PIM mode exiting code including a second back-to-back address sequence associated with the sequential write commands, the PIM mode exiting code being stored in the memory device. 
     
     
       14. The method of  claim 13 , further comprising:
 receiving second addresses sequentially; 
 comparing the second back-to-back address sequence of the PIM mode exiting code with the second addresses; and 
 deactivating the processing mode selection signal when the second addresses match the second back-to-back address sequence of the PIM mode exiting code. 
 
     
     
       15. The method of  claim 13 , further comprising entering a normal mode in response to the deactivation of the processing mode selection signal. 
     
     
       16. The method of  claim 9 , wherein the memory device supports a double data rate (DDR) protocol or a low power double data rate (LPDDR) protocol. 
     
     
       17. A memory system comprising:
 a memory device configured to perform an internal processing operation using a processing-in-memory (PIM) engine in an internal processing mode; and 
 a memory controller configured to transmit first addresses sequentially along with sequential write commands to the memory device; and 
 wherein the memory device comprises: 
 a memory cell array including a first memory region and a second memory region; 
 a mode selector circuit configured to store a PIM mode entering code that includes a first back-to-back address sequance associated with the sequential write commands, compare bit values of the first addresses with bit values of the first back-to-back address sequence of the PIM mode entering code, and activate a processing mode selection signal for controlling the memory device to enter the internal processing mode when the first addresses are received sequantially along with the sequential write commands and a result of the compare indicates the bit values of the first addresses match the bit values of the first back-to-back address sequence of the PIM mode entering code associated with the sequential write commands; and 
 the PIM engine configured to perform the internal processing operation on the first memory region after entering the internal processing mode. 
 
     
     
       18. The memory system of  claim 17 , wherein the memory controller is further configured to transmit second addresses sequentially along with sequential write commands to the memory device, and the mode selector circuit is further configured to store a PIM mode exiting code associated with the sequential write commands, compare the second addresses with the PIM mode exiting code, and deactivate the processing mode selection signal for controlling the memory device to exit the internal processing mode when the second addresses match addresses of the PIM mode exiting code associated with the sequential write commands. 
     
     
       19. The memory system of  claim 17 , wherein the memory device further comprises a command converter circuit configured to convert a read command into an internal processing read command in the internal processing mode, and the PIM engine is further configured to read internal processing data from memory cells of the first memory region in response to the internal processing read command and perform the internal processing operation by using the read internal processing data. 
     
     
       20. The memory system of  claim 19 , wherein the command converter circuit is further configured to convert a write command into an internal processing write command in the internal processing mode, and the PIM engine is further configured to write internal processing data obtained as a processing result of performing the internal processing operation, to memory cells of the first memory region, in response to the internal processing write command.