Thin film transistor and thin film transistor array panel including the same

Abstract

A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

What is claimed is: 
     
       1. A display device, comprising:
 a substrate; 
 a first insulating layer disposed on the substrate; 
 a light blocking layer disposed between the substrate and the first insulating layer; 
 a data line disposed between the substrate and the first insulating layer; 
 a semiconductor layer disposed on the first insulating layer, the semiconductor layer including a first region, a second region, and a channel region between the first region and the second region; 
 a second insulating layer disposed on the semiconductor layer; 
 a gate electrode disposed on the second insulating layer; 
 a third insulating layer disposed on the gate electrode; and 
 a first electrode disposed on the third insulating layer, 
 wherein the third insulating layer has a first opening on the first region, and the first electrode is electrically connected to the first region through the first opening. 
 
     
     
       2. The display device of  claim 1 , wherein the third insulating layer contacts a lateral surface of the gate electrode and a lateral surface of the second insulating layer. 
     
     
       3. The display device of  claim 1 , further comprising a second electrode disposed on the third insulating layer,
 wherein the third insulating layer has a second opening on the data line, and 
 wherein the second electrode is electrically connected to the data line through the second opening. 
 
     
     
       4. The display device of  claim 1 , further comprising a fourth insulating layer disposed on the third insulating layer. 
     
     
       5. The display device of  claim 1 , wherein the channel region overlaps the light blocking layer. 
     
     
       6. The display device of  claim 1 , wherein at least one of the first insulating layer or the second insulating layer comprises an insulating oxide. 
     
     
       7. The display device of  claim 1 , wherein a length of the second insulating layer in a direction is longer than a length of the gate electrode in the direction in a plan view. 
     
     
       8. The display device of  claim 1 , wherein the third insulating layer contacts a portion of an upper surface of the second insulating layer. 
     
     
       9. The display device of  claim 1 , wherein the data line comprises a conductive material including at least one selected from aluminum, aluminum, silver, copper, molybdenum, chromium, tantalum, or titanium. 
     
     
       10. The display device of  claim 1 , wherein the first opening overlaps the light blocking layer in a plan view. 
     
     
       11. A display device, comprising:
 a substrate; 
 a first insulating layer disposed on the substrate; 
 a first metal layer disposed between the substrate and the first insulating layer; 
 a semiconductor layer disposed on the first insulating layer, the semiconductor layer including a first doping region, a second doping region, and a channel region between the first doping region and the second doping region; 
 a second insulating layer disposed on the semiconductor layer; 
 a gate electrode disposed on the second insulating layer; 
 a third insulating layer disposed on the gate electrode; and 
 a first electrode disposed on the third insulating layer, 
 wherein the third insulating layer has a first opening on the first doping region, and the first electrode is electrically connected to the first doping region through the first opening, 
 wherein the first insulating layer has a second opening, and 
 wherein a length of the second insulating layer in a direction is longer than a length of the gate electrode in the direction in a plan view. 
 
     
     
       12. The display device of  claim 11 , further comprising a fourth insulating layer disposed on the third insulating layer. 
     
     
       13. The display device of  claim 11 , wherein the channel region overlaps the first metal layer. 
     
     
       14. The display device of  claim 11 , wherein at least one of the first insulating layer or the second insulating layer comprises an insulating oxide. 
     
     
       15. The display device of  claim 11 , wherein the first metal layer comprises a conductive material including at least one selected from aluminum, aluminum, silver, copper, molybdenum, chromium, tantalum, or titanium. 
     
     
       16. The display device of  claim 11 , wherein the first opening and the second opening overlaps the first metal layer in the plan view. 
     
     
       17. A display device, comprising:
 a substrate; 
 a first insulating layer disposed on the substrate; 
 a light blocking layer disposed between the substrate and the first insulating layer; 
 a data line disposed between the substrate and the first insulating layer; 
 a semiconductor layer disposed on the first insulating layer, the semiconductor layer including a first region, a second region, and a channel region between the first region and the second region; 
 a second insulating layer disposed on the semiconductor layer; 
 a gate electrode disposed on the second insulating layer; 
 a third insulating layer disposed on the gate electrode; and 
 a first electrode disposed on the third insulating layer, 
 wherein the third insulating layer has a first opening on the first region, and the first electrode is electrically connected to the first region through the first opening, 
 wherein the light blocking layer and the data line comprises a same material as each other, 
 wherein the third insulating layer contacts a lateral surface of the gate electrode and a lateral surface of the second insulating layer, 
 wherein a length of the second insulating layer in a direction is longer than a length of the gate electrode in the direction in a plan view, and 
 wherein the third insulating layer contacts a portion of an upper surface of the second insulating layer. 
 
     
     
       18. The display device of  claim 17 , further comprising a second electrode disposed on the third insulating layer,
 wherein the third insulating layer has a second opening on the data line, and 
 wherein the second electrode is electrically connected to the data line through the second opening. 
 
     
     
       19. The display device of  claim 17 , further comprising a fourth insulating layer disposed on the third insulating layer. 
     
     
       20. The display device of  claim 17 , wherein the channel region overlaps the light blocking layer. 
     
     
       21. The display device of  claim 17 , wherein at least one of the first insulating layer or the second insulating layer comprises an insulating oxide. 
     
     
       22. The display device of  claim 17 , wherein the data line comprises a conductive material including at least one selected from aluminum, aluminum, silver, copper, molybdenum, chromium, tantalum, or titanium. 
     
     
       23. The display device of  claim 17 , wherein the first opening overlaps the light blocking layer in the plan view.