Arithmetic processing device and arithmetic processing method

Abstract

An arithmetic processing device includes an instruction storage configured to store an arithmetic instruction and a data cache configured to cache a calculation result of the arithmetic instruction. A plurality of floating-point registers arranged on a side of the instruction storage is configured to store a register value used for executing the arithmetic instruction transferred from the instruction storage, and a plurality of floating point calculation circuits arranged on a side of the data cache is configured to perform a floating-point operation based on the arithmetic instruction, wherein a number of cycles is one when the register value is transferred from the instruction storage to one or more floating-point registers, among the plurality of floating point registers, arranged in positions closest in distance to the instruction storage.

What is claimed is: 
     
       1. An arithmetic processing device, comprising:
 an instruction storage configured to store an arithmetic instruction; 
 a data cache configured to cache a calculation result of the arithmetic instruction; 
 a plurality of floating-point registers arranged on a side of the instruction storage and configured to store a register value used for executing the arithmetic instruction transferred from the instruction storage; and 
 a plurality of floating point calculation circuits arranged on a side of the data cache and configured to perform a floating-point operation based on the arithmetic instruction, 
 wherein a number of cycles is one when the register value is transferred from the instruction storage to one or more floating-point registers, among the plurality of floating point registers, arranged in positions closest in distance to the instruction storage. 
 
     
     
       2. The arithmetic processing device according to  claim 1 ,
 wherein the above one or more floating-point registers among the plurality of floating-point registers, and one or more floating-point calculation circuits arranged in positions closest in distance to the data cache among the plurality of floating-point calculation circuits are used for executing the arithmetic instruction. 
 
     
     
       3. The arithmetic processing device according to  claim 1 ,
 wherein, after a load instruction or a store instruction is executed, the arithmetic instruction is executed. 
 
     
     
       4. An arithmetic processing method comprising:
 storing an arithmetic instruction to an instruction storage; 
 caching a calculation result of the arithmetic instruction to a data cache; 
 storing a register value used for executing the arithmetic instruction transferred from the instruction storage to a plurality of floating-point registers arranged on a side of the instruction storage and configured to; and 
 performing a floating-point operation based on the arithmetic instruction by a plurality of floating-point calculation circuits arranged on a side of the data cache, 
 wherein a number of cycles is one when the register value is transferred from the instruction storage to one or more floating-point registers, among the plurality of floating-point registers, arranged in positions closest in distance to the instruction storage. 
 
     
     
       5. The arithmetic processing method according to  claim 4 ,
 wherein the above one or more floating-point registers among the plurality of floating-point registers, and one or more floating-point calculation circuits arranged in positions closest in distance to the data cache among the plurality of floating-point calculation circuits are used for executing the arithmetic instruction. 
 
     
     
       6. The arithmetic processing method according to  claim 4 ,
 wherein, after a load instruction or a store instruction is executed, the arithmetic instruction is executed.