Rule check violation prediction systems and methods

Abstract

Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.

The invention claimed is: 
     
       1. A method, comprising:
 generating, by design rule check (DRC) machine learning circuitry, information associated with a plurality of routing congestion patterns, based on past data indicative of presence and location of DRC violations in placement layouts after routing has been performed, the plurality of routing congestion patterns including regions where a plurality of systematic DRC violations are predicted or determined to occur, the information including probability information indicating probabilities of one or more systematic DRC violations occurring in the plurality of routing congestion patterns; 
 predicting, by DRC violation prediction circuitry and prior to routing a placement layout of a semiconductor circuit design, for each of a plurality of regions of the placement layout, whether one or more systematic DRC violations would be present due to routing of the placement layout based at least in part on the information associated with the plurality of routing congestion patterns; and 
 routing the placement layout in response to predicting that no systematic DRC violations would be present due to routing of the placement layout. 
 
     
     
       2. The method of  claim 1  wherein the routing the placement layout includes routing the placement layout in response to predicting that, for each of the plurality of regions, a number of predicted systematic DRC violations that would be present due to routing of the placement layout is below a threshold value. 
     
     
       3. The method of  claim 1 , further comprising:
 adjusting the placement layout by increasing a spacing between cells of at least one region of the placement layout, in response to the DRC violation prediction circuitry predicting that one or more systematic DRC violations would be present in the at least one region of the placement layout due to routing of the placement layout. 
 
     
     
       4. The method of  claim 3 , further comprising:
 routing the adjusted placement layout. 
 
     
     
       5. The method of  claim 1 , further comprising:
 deriving locations of one or more systematic DRC clusters in response to predicting that one or more systematic DRC violations would be present due to routing of the placement layout. 
 
     
     
       6. The method of  claim 1  further comprising:
 receiving the placement layout, including accessing, by the DRC violation prediction circuitry, a placement database which stores the placement layout. 
 
     
     
       7. The method of  claim 1 , further comprising:
 storing the information associated with the plurality of routing congestion patterns in a processed pattern database. 
 
     
     
       8. The method of  claim 1 , further comprising:
 accessing, by the DRC machine learning circuitry, a systematic DRC database which stores information associating systematic DRC violations with at least one of a placement layout or a placement layout region; and 
 generating, by the DRC machine learning circuitry, the information associated with the plurality of routing congestion patterns based on the information stored in the systematic DRC database. 
 
     
     
       9. The method of  claim 1 , further comprising:
 generating, by the DRC machine learning circuitry, the probability information by performing a probability mass function transformation on the information stored in the systematic DRC database. 
 
     
     
       10. The method of  claim 9 , further comprising:
 identifying, by the DRC machine learning circuitry, systematic DRC clusters in the processed patterns based on the probability information. 
 
     
     
       11. The method of  claim 10  wherein the identifying systematic DRC clusters in the processed patterns includes identifying the systematic DRC clusters in the processed patterns based on a cosine similarity between one or more features in the processed patterns. 
     
     
       12. The method of  claim 1 , further comprising:
 receiving, by the DRC violation prediction circuitry, the placement layout. 
 
     
     
       13. The method of  claim 1 , further comprising:
 inspecting, by the DRC violation prediction circuitry, placement data associated with each of a plurality of regions of the placement layout. 
 
     
     
       14. A method, comprising:
 generating, by design rule check (DRC) machine learning circuitry, information associated with a plurality of routing congestion patterns, based on past data indicative of presence and location of DRC violations in placement layouts after routing has been performed, the plurality of routing congestion patterns including regions where a plurality of systematic DRC violations are predicted or determined to occur, the information including probability information indicating probabilities of one or more systematic DRC violations occurring in the plurality of routing congestion patterns; 
 predicting, by DRC violation prediction circuitry and prior to routing a placement layout of a semiconductor circuit design, for each of a plurality of regions of the semiconductor circuit design, whether one or more systematic DRC violations would be present due to routing of the placement layout based at least in part on the information associated with the plurality of routing congestion patterns; and 
 storing, by a placement database, the placement data. 
 
     
     
       15. The method of  claim 14 , the receiving the placement layout includes accessing, by the DRC violation prediction circuitry, a placement database which stores the placement layout. 
     
     
       16. The method of  claim 14 , further comprising:
 generating, by the DRC machine learning circuitry, information associated with a plurality of routing congestion patterns, based on past data indicative of presence and location of DRC violations in placement layouts after routing has been performed, the plurality of routing congestion patterns including regions where a plurality of systematic DRC violations are predicted or determined to occur, 
 wherein the predicting whether one or more systematic DRC violations would be present due to routing of the placement layout includes predicting whether one or more systematic DRC violations would be present due to routing of the placement layout based at least in part on the information associated with the plurality of routing congestion patterns. 
 
     
     
       17. The method of  claim 14 , further comprising:
 storing the information associated with the plurality of routing congestion patterns in a processed pattern database. 
 
     
     
       18. The method of  claim 17 , further comprising:
 accessing, by the DRC machine learning circuitry, a systematic DRC database which stores information associating systematic DRC violations with at least one of a placement layout or a placement layout region; and 
 generating, by the DRC machine learning circuitry, the information associated with the plurality of routing congestion patterns based on the information stored in the systematic DRC database. 
 
     
     
       19. A method, comprising:
 generating, by design rule check (DRC) machine learning circuitry, information associated with a plurality of routing congestion patterns, based on past data indicative of presence and location of DRC violations in placement layouts after routing has been performed, the plurality of routing congestion patterns including regions where a plurality of systematic DRC violations are predicted or determined to occur, the information including probability information indicating probabilities of one or more systematic DRC violations occurring in the plurality of routing congestion patterns, 
 predicting, by DRC violation prediction circuitry and prior to routing a placement layout of a semiconductor circuit design, for each of a plurality of regions of the placement layout, whether one or more systematic DRC violations would be present due to routing of the placement layout based at least in part on the information associated with the plurality of routing congestion patterns based at least in part on the information associated with the plurality of routing congestion patterns; and 
 routing the placement layout in response to predicting that, for each of the plurality of regions, a number of predicted systematic DRC violations that would be present due to routing of the placement layout is below a threshold value. 
 
     
     
       20. The method of  claim 19 , further comprising:
 adjusting the placement layout by increasing a spacing between cells of at least one region of the placement layout, in response to the DRC violation prediction circuitry predicting that one or more systematic DRC violations would be present in the at least one region of the placement layout due to routing of the placement layout.