Oscillator circuit arrangement

Abstract

An oscillator circuit arrangement includes a switched capacitor circuit at least one capacitor selectively coupled to one of a supply terminal and a terminal for ground potential. A chopper circuit is disposed between the switched capacitor circuit and a comparator. The chopper circuit selectively couples one of input terminals and a reference potential terminal to its output terminals. A buffer circuit is coupled to the output of the comparator circuit. The buffer circuit is connected to the switched capacitor circuit and to the chopper circuit to control selective coupling operations therein.

The invention claimed is: 
     
       1. An oscillator circuit arrangement, comprising:
 a switched capacitor circuit having at least one output terminal, a supply terminal and a terminal for ground potential, comprising at least one capacitor having at least one terminal, the switched capacitor circuit configured to selectively couple the at least one terminal to one of the supply terminal and the terminal for ground potential, the output terminal coupled to the at least one capacitor; 
 a chopper circuit having a first input terminal and a second input terminal connected to the switched capacitor circuit, a terminal for a reference potential, a first output terminal and a second output terminal, the chopper circuit configured to selectively couple the first output terminal to one of the first input terminal and the terminal for a reference potential and to couple the second output terminal to one of the second input terminal and the terminal for a reference potential; 
 a comparator circuit having input terminals connected to the output terminals of the chopper circuit and an output terminal; 
 a buffer circuit including at least one buffer connected to the output terminal of the comparator circuit, to the switched capacitor circuit to control selective coupling of the at least one capacitor and to the chopper circuit ( 400 ) to control selective coupling of the first and second output terminals; and 
 an output terminal connected to the buffer circuit to supply a clock signal, 
 wherein the switched capacitor circuit comprises a fifth, a sixth, a seventh and an eighth switch, wherein the at least one terminal of the at least one capacitor is connected to the output terminal of the switched capacitor circuit through the sixth switch and to the terminal for ground potential through the seventh switch, wherein another terminal of the at least one capacitor is connected to the output terminal of the switched capacitor circuit through the fifth switch and to the terminal for ground potential through the eighth switch, wherein the fifth and seventh switches are operated in phase with each other and the sixth and eighth switches are operated out of phase or complementary with the fifth and seventh switches. 
 
     
     
       2. The oscillator circuit arrangement of  claim 1 , wherein the chopper circuit is configured to couple the first input terminal of the chopper circuit to the first output terminal of the chopper circuit and the terminal for a reference potential to the second output terminal of the chopper circuit and, subsequently, to couple the second input terminal of the chopper circuit to the second output terminal of the chopper circuit and the terminal for a reference potential to the first output terminal of the chopper circuit. 
     
     
       3. The oscillator circuit arrangement of  claim 1 , wherein the chopper circuit comprises a first, a second, a third and a fourth switch, the first switch connected between the first input terminal of the chopper circuit and the first output terminal of the chopper circuit, the second switch connected between the terminal for a reference potential and the first output terminal of the chopper circuit, the third switch connected between the terminal for a reference potential and the second output terminal of the chopper circuit, the fourth switch connected between the second input terminal of the chopper circuit and the second output terminal of the chopper circuit, the first and the third switches operated in phase with each other and operated out of phase or complementary with the second and fourth switches. 
     
     
       4. The oscillator circuit arrangement of  claim 3 , wherein the first and the third switches of the chopper circuit are controlled by the at least one buffer of the buffer circuit and the second and fourth switches are controlled complementary to the first and third switches. 
     
     
       5. The oscillator circuit arrangement of  claim 3 , wherein the first and the third switches of the chopper circuit are controlled by an output signal of the at least one buffer of the buffer circuit and the second and fourth switches are controlled by an input signal to the at least one buffer of the buffer circuit. 
     
     
       6. The oscillator circuit arrangement of  claim 1 , wherein the fifth and the seventh switches of the switched capacitor circuit are controlled by an output signal of the at least one buffer of the buffer circuit and the sixth and the eighth switches are controlled by an input signal to the at least one buffer. 
     
     
       7. The oscillator circuit arrangement of  claim 1 , the switched capacitor circuit further comprising another capacitor connected between the output terminal of the switched capacitor circuit and the terminal for ground potential, wherein the supply terminal is connected to the output terminal of the switched capacitor circuit. 
     
     
       8. The oscillator circuit arrangement of  claim 1 , the switched capacitor circuit further comprising another capacitor and another output terminal, the other capacitor connected to the other output terminal of the switched capacitor circuit, wherein the supply terminal is coupled to the at least one capacitor and the other capacitor through switches. 
     
     
       9. The oscillator circuit arrangement of  claim 1 , further comprising a constant current source connected to the supply terminal of the switched capacitor circuit. 
     
     
       10. The oscillator circuit arrangement of  claim 9 , further comprising a reference voltage generator comprising another constant current source and a resistor serially connected with the other constant current source, wherein a node disposed between the other constant current source and the resistor is connected to the terminal for a reference potential of the chopper circuit. 
     
     
       11. The oscillator circuit arrangement of  claim 1 , further comprising a resistor connected to the supply terminal of the switched capacitor circuit. 
     
     
       12. The oscillator circuit arrangement of  claim 11 , further comprising a voltage divider connected between a terminal for a supply potential and the terminal for ground potential, an output terminal of the voltage divider connected to the terminal for a reference potential of the chopper circuit. 
     
     
       13. An electronic device, comprising:
 a digital circuit portion configured to operate clockwise in response to a clock signal; and 
 the oscillator circuit arrangement according to  claim 1 , wherein the clock signal is derived from the clock signal supplied at the output terminal of the oscillator circuit.