Vertical access line in a folded digitline sense amplifier

Abstract

The present disclosure includes apparatuses and methods for vertical access line in a folded digitline sense amplifier. An example apparatus includes an array of memory cells. The memory cells form active areas having adjacent access devices, each access device having a first source/drain region and a second source/drain region separated by a channel region and a gate opposing the channel region. A pair of adjacent memory cells can share a digitline contact at the second source/drain region. A storage node contact can be coupled to respective first source/drain regions and each gate can be connected to vertically oriented access lines formed on opposing side of a depletion region to each access device. An insulator material can be patterned between adjacent digitlines to isolate adjacent memory cells.

What is claimed is: 
     
       1. An apparatus, comprising:
 an array of memory cells, wherein
 the memory cells form active areas having adjacent access devices, each access device having a first source/drain region and a second source/drain region separated by a channel region and a gate opposing the channel region; 
 a pair of adjacent memory cells share a digitline contact at the respective second source/drain regions and each respective storage node of the pair of adjacent memory cells is coupled to the respective first source/drain regions; and 
 each gate is connected to vertically oriented access lines formed on opposing side of a depletion region to each access device; 
 
 a sense amplifier coupled to digitlines in the array according to a folded digitline sense amplifier architecture; and 
 an insulator material patterned between adjacent digitlines to isolate adjacent memory cells. 
 
     
     
       2. The apparatus of  claim 1 , wherein each memory cell is formed within four lithographic features squared (4F 2 ). 
     
     
       3. The apparatus of  claim 1 , wherein each active area is at an angle of a range between 40-50 degrees to an orientation of the vertically oriented access lines and the digitlines. 
     
     
       4. The apparatus of  claim 3 , wherein each successive active area is alternately angled relative to an adjacent active area. 
     
     
       5. The apparatus of  claim 1 , wherein the memory cells are dynamic random access memory (DRAM) cells. 
     
     
       6. The apparatus of  claim 1 , wherein the vertically oriented access lines and gates are formed using atomic layer deposition techniques. 
     
     
       7. An apparatus, comprising:
 an array of memory cells, wherein
 each memory cell is formed within four lithographic features squared (4F 2 ) according to a folded digitline sense amplifier architecture; 
 the memory cells include alternately angled active areas having adjacent access devices, each access device having a first source/drain region and a second source/drain region separated by a channel region and a gate opposing the channel region; 
 a pair of adjacent memory cells share a digitline contact at the respective second source/drain regions and a each respective storage node of the pair of adjacent memory cells is coupled to the respective first source/drain regions; and 
 the gate is connected to vertically oriented access lines formed on opposing side of a depletion region to each access device; 
 
 a sense amplifier coupled to digitlines in the array; and 
 an insulator material formed between adjacent digitlines to separate adjacent memory cells. 
 
     
     
       8. The apparatus of  claim 7 , wherein the gate is a conductive spacer. 
     
     
       9. The apparatus of  claim 7 , wherein the gate controls current flow between the digitline contact and each access device. 
     
     
       10. The apparatus of  claim 7 , wherein each vertically oriented access line passes over alternating active areas. 
     
     
       11. The apparatus of  claim 10 , wherein each vertically oriented access line activates one memory cell of the pair of adjacent memory cells. 
     
     
       12. The apparatus of  claim 10 , wherein one of the adjacent digitlines remains at a reference voltage. 
     
     
       13. The apparatus of  claim 7 , wherein the gate has an aspect ratio (AR) of the height to width being in a range of from 5:1 to 15:1. 
     
     
       14. The apparatus of  claim 7 , wherein the digitline contact is adjacent the depletion region. 
     
     
       15. An apparatus, comprising:
 a memory cell having a size of four lithographic features squared (4F 2 );
 wherein the memory cell includes a vertical gate opposing a channel region; 
 wherein the channel region is coupled a storage node at first source/drain region and is coupled to a digitline at a second source/drain region; 
 wherein an active area of the memory cell is at an angle between 20° and 65° with respect to the digitline; 
 wherein an insulator material isolates the memory cell from an adjacent memory cell; and 
 wherein the memory cell is coupled to the digitline having a folded digitline sense amplifier architecture. 
 
 
     
     
       16. The apparatus of  claim 15 , wherein the digitline is approximately orthogonal to the vertical gate. 
     
     
       17. The apparatus of  claim 15 , the memory cells include two lithographic features (2F) on a vertical axis crossed with two lithographic features on a horizontal axis to produce the memory cell within four lithographic features squared (4F 2 ). 
     
     
       18. The apparatus of  claim 15 , wherein the vertical gate is formed above an active area of the memory cell and on a sidewall of a depletion region of the memory cell.