Method of fabricating metal gate transistor

Abstract

A method of fabricating a metal gate transistor includes providing a substrate. Then, a high-k dielectric layer is formed to cover the substrate. Later, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. After the ion implantation process, a polysilicon gate is formed on the high-k dielectric layer. Next, an interlayer dielectric layer is formed to cover the substrate and the polysilicon gate. Finally, the polysilicon gate is replaced by a metal gate.

What is claimed is: 
     
       1. A method of fabricating a metal gate transistor, comprising:
 providing a substrate; 
 forming a high-k dielectric layer covering the substrate; 
 performing an ion implantation process to implant fluoride ions into the high-k dielectric layer; 
 after the ion implantation process, forming a polysilicon gate on the high-k dielectric layer; 
 forming an interlayer dielectric layer covering the substrate and the polysilicon gate; and 
 replacing the polysilicon gate by a metal gate. 
 
     
     
       2. The method of fabricating a metal gate transistor of  claim 1 , wherein a gate dielectric layer is disposed between the high-k dielectric layer and the substrate. 
     
     
       3. The method of fabricating a metal gate transistor of  claim 2 , wherein while performing the ion implantation process, the fluoride ions are implanted into the gate dielectric layer. 
     
     
       4. The method of fabricating a metal gate transistor of  claim 2 , wherein the gate dielectric layer comprises silicon oxide, silicon nitride, silicon carbide nitride, silicon oxynitride or silicon carbide oxynitride. 
     
     
       5. The method of fabricating a metal gate transistor of  claim 1 , wherein the high-k dielectric layer comprises Al 2 O 3 , ZrO 2 , barium strontium titanate (BST), lead zirconate titanate (PZT), ZrSiO 2 , HfSiO 2 , HfSiON or TaO 2 . 
     
     
       6. The method of fabricating a metal gate transistor of  claim 1 , wherein two source/drain doping regions are disposed in the substrate at two sides of the polysilicon gate.