ReRAM memory array that includes ReRAM memory cells having a ReRAM device and two series-connected select transistors that can be selected for erasing

Abstract

A ReRAM memory array includes ReRAM memory cells having two series-connected select transistors connected in series with a ReRAM device. When ReRAM memory cell(s) are selected for erasing, the bit line coupled to the ReRAM memory cell(s) to be erased is biased at a first voltage potential. The source line coupled to the ReRAM memory cell(s) to be erased is biased at a second voltage potential greater than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to erase the ReRAM device. The gates of the series-connected select transistors of the ReRAM memory cell(s) to be erased are supplied with positive voltage pulses. The gates of the series-connected select transistors of the ReRAM memory cell(s) unselected for erasing are supplied with a voltage potential insufficient to turn them on.

What is claimed is: 
     
       1. A ReRAM memory array arranged as rows and columns forming intersections, the ReRAM memory array comprising:
 a plurality of ReRAM memory cells, respective ReRAM memory cells of the plurality of ReRAM memory cells include a ReRAM device having a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and include two series-connected select transistors connected in series with the ReRAM device, respective series-connected select transistors of the two series-connected select transistors having a gate connected to a separate control line, 
 wherein respective columns of the array include a bit line connected to a first node of respective ReRAM memory cells in the respective column and a decoded source line connected to a second node of respective ReRAM memory cells in the respective column, 
 wherein, when one or more respective ReRAM memory cell of the plurality of ReRAM memory cells is selected for erasing, biasing the bit line coupled to the one or more respective ReRAM memory cell selected for erasing at a first voltage potential, biasing the source line coupled to the one or more respective ReRAM memory cell selected for erasing at a second voltage potential greater than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to erase the ReRAM device in the one or more respective ReRAM memory cell selected for erasing, and supplying the gates of the series-connected select transistors of the one or more respective ReRAM memory cell selected for erasing with positive voltage pulses; and 
 wherein, when one or more respective ReRAM memory cell of the plurality of ReRAM memory cells is unselected for erasing, supplying the gate of the one of the series-connected select transistors having its drain connected to the second electrode of the one or more respective ReRAM memory cell unselected for erasing with a voltage potential insufficient to turn it on. 
 
     
     
       2. The ReRAM memory array of  claim 1  wherein the two series-connected select transistors are n-channel transistors. 
     
     
       3. The ReRAM memory array of  claim 1  wherein respective rows of the array include a first word line connected to the control line of a first one of the two series-connected select transistors of respective ReRAM memory cells in the row and a second word line connected to the control line of a second one of the two series-connected select transistors of respective ReRAM memory cells in the row. 
     
     
       4. The ReRAM memory array of  claim 1  wherein the first ion-source electrode is connected to the first node and the two series-connected select transistors comprise a first n-channel select transistor connected in series with a second n-channel select transistor between the second electrode of the ReRAM device and the second node, the first n-channel select transistor having a gate connected to a first select node and the second n-channel select transistor having a gate connected to a second select node. 
     
     
       5. The ReRAM memory array of  claim 4  wherein respective rows of the array include a first word line connected to the gate of the first n-channel select transistor of respective ReRAM memory cells in the row and a second word line connected to the gate of the second n-channel select transistor of respective ReRAM memory cells in the row. 
     
     
       6. The ReRAM memory array of  claim 1  wherein the gates of the respective series-connected select transistors of the one or more respective ReRAM memory cell unselected for erasing are supplied with a voltage potential selected to divide the voltage evenly between the two series-connected select transistors of the one or more respective ReRAM memory cell unselected for erasing.