Dynamic management of a memory firewall

Abstract

In embodiments, a system includes a first and a second processing unit, a memory, and a firewall device. The first processing unit operates in a secure mode and generates memory access requests having a secure level. The second processing unit operates in a non-secure mode and generates memory access requests having a non-secure level. The memory includes a first memory area that can be shared between the first and second processing units. The firewall device includes a first firewall circuit with a first configuration authorizing access to the first memory area in the presence of a secure or non-secure level access request. The firewall circuit includes a second configuration prohibiting access to the first memory area in the presence of a secure level access request and authorizing access to the first memory area only in the presence of a non-secure level access request.

What is claimed is: 
     
       1. A system, comprising:
 a first processing unit configured to:
 operate in a secure mode, and 
 generate memory access requests having a secure level; 
 
 a second processing unit configured to:
 operate in a non-secure mode, and 
 generate memory access requests having a non-secure level; 
 
 a memory storage having a first memory area shared between the first processing unit and the second processing unit; and 
 a firewall device coupled between the memory storage, the first processing unit, and the second processing unit, the firewall device comprising a first firewall circuit associated with the first memory area, the first firewall circuit having a first configuration and a second configuration configurable by the second processing unit, 
 wherein in the first configuration, access to the first memory area is authorized in response to a presence of a secure level access request or a non-secure level access request, and 
 wherein in the second configuration, access to the first memory area is prohibited in response to the presence of a secure level access request and access to the first memory area is authorized in response to the presence of the non-secure level access request. 
 
     
     
       2. The system of  claim 1 , wherein the memory storage comprises a memory region allocated to the second processing unit, the memory region containing the first memory area, and wherein the second processing unit is configured to define the first memory area within the memory region. 
     
     
       3. The system of  claim 2 , wherein the memory storage comprises a second memory area allocated to the first processing unit, wherein the memory storage comprises a third memory area reserved for the second processing unit, and wherein the firewall device comprises:
 a second firewall circuit associated with the second memory area, the second firewall circuit configured to authorize access to the second memory area only in response to a presence of secure level requests, and 
 a third firewall circuit associated with the third memory area, the third firewall circuit configured to authorize access to the third memory area only in response to a presence of non-secure level requests. 
 
     
     
       4. The system of  claim 3 , wherein the memory access requests comprises indications representative of the secure level or the non-secure level, wherein the second firewall circuit and the third firewall circuit comprises:
 sets of registers, respectively, associated with the first memory area, the second memory area, and the third memory area, the sets of registers comprising information data representative of secure access rights, non-secure access rights, or a combination thereof, to the first memory area, the second memory area, or the third memory area; and 
 a verification circuit configured to:
 compare an indication of a request for access to an associated memory area with the information data contained in a corresponding set of registers, and 
 authorize or prohibit access to the associated memory area based on the comparison. 
 
 
     
     
       5. The system of  claim 4 , wherein contents of a register associated with the first memory area is modifiable based on a command from the second processing unit. 
     
     
       6. The system of  claim 1 , further comprising:
 a memory management circuit coupled between the firewall device, the first processing unit, and the second processing unit, the memory management circuit configured to not degrade the security level of a secure level access request. 
 
     
     
       7. The system of  claim 1 , further comprising a processor having:
 a first operating system configured to operate in a secure level execution context by the first processing unit; and 
 a second operating system configured to operate in a non-secure level execution context by the second processing unit. 
 
     
     
       8. The system of  claim 1 , wherein the system is incorporated within a system on a chip (SoC) circuit. 
     
     
       9. A method, comprising:
 operating, a first processing unit, in a secure mode; 
 generating, by the first processing unit, memory access requests having a secure level; 
 operating, a second processing unit, in a non-secure mode; 
 generating, by the second processing unit, memory access requests having a non-secure level; and 
 configuring, by the second processing unit, a first firewall circuit in a first configuration or a second configuration, the first firewall circuit being a circuit of a firewall device, the first firewall circuit associated with a first memory area of a memory storage, the first memory area shared between the first processing unit and the second processing unit, 
 wherein in the first configuration, access to the first memory area is authorized in response to a presence of a secure level access request or a non-secure level access request, and 
 wherein in the second configuration, access to the first memory area is prohibited in response to the presence of a secure level access request and access to the first memory area is authorized in response to the presence of the non-secure level access request. 
 
     
     
       10. The method of  claim 9 , wherein the memory storage comprises a memory region allocated to the second processing unit, the memory region containing the first memory area, and wherein the second processing unit is configured to define the first memory area within the memory region. 
     
     
       11. The method of  claim 10 , wherein the memory storage comprises a second memory area allocated to the first processing unit, wherein the memory storage comprises a third memory area reserved for the second processing unit, and wherein the firewall device comprises a second firewall circuit associated with the second memory area, wherein the firewall device comprises a third firewall circuit associated with the third memory area, the method further comprising:
 authorizing access, by the second firewall circuit, to the second memory area only in response to a presence of secure level requests, and 
 authorizing access, by the third firewall circuit, to the third memory area only in response to a presence of non-secure level requests. 
 
     
     
       12. The method of  claim 9 , further comprising:
 preventing a degradation, by a memory management circuit, of the security level of a secure level access request, the memory management circuit coupled between the firewall device, the first processing unit, and the second processing unit. 
 
     
     
       13. The method of  claim 9 , further comprising:
 operating, by a first operating system of the first processing unit, a secure level execution context; and 
 operating, by a second operating system of the second processing unit, a non-secure level execution context. 
 
     
     
       14. The method of  claim 9 , wherein the first processing unit, the second processing unit, the memory storage, and the firewall device are part of a system incorporated within a system on a chip (SoC) circuit. 
     
     
       15. A system on a chip (SoC) circuit, comprising:
 a first processing unit configured to:
 operate, using a first operating system, a secure level execution context in a secure mode, and 
 generate memory access requests having a secure level; 
 
 a second processing unit configured to:
 operate, using a second operating system, a non-secure level execution context in a non-secure mode, and 
 generate memory access requests having a non-secure level; 
 
 a memory storage having a first memory area shared between the first processing unit and the second processing unit; and 
 a firewall device comprising a first firewall circuit associated with the first memory area, the first firewall circuit configurable by the second processing unit, 
 wherein in a first configuration, access to the first memory area is authorized in response to a presence of a secure level access request or a non-secure level access request, and 
 wherein in a second configuration, access to the first memory area is prohibited in response to the presence of a secure level access request and access to the first memory area is authorized in response to the presence of the non-secure level access request. 
 
     
     
       16. The SoC circuit of  claim 15 , wherein the memory storage comprises a memory region allocated to the second processing unit, the memory region containing the first memory area, and wherein the second processing unit is configured to define the first memory area within the memory region. 
     
     
       17. The SoC circuit of  claim 16 , wherein the memory storage comprises a second memory area allocated to the first processing unit, wherein the memory storage comprises a third memory area reserved for the second processing unit, and wherein the firewall device comprises:
 a second firewall circuit associated with the second memory area, the second firewall circuit configured to authorize access to the second memory area only in response to a presence of secure level requests, and 
 a third firewall circuit associated with the third memory area, the third firewall circuit configured to authorize access to the third memory area only in response to a presence of non-secure level requests. 
 
     
     
       18. The SoC circuit of  claim 17 , wherein the memory access requests comprises indications representative of the secure level or the non-secure level, wherein the first firewall circuit, the second firewall circuit, and the third firewall circuit comprises:
 sets of registers, respectively, associated with the first memory area, the second memory area, and the third memory area, the sets of registers comprising information data representative of secure access rights, non-secure access rights, or a combination thereof, to the first memory area, the second memory area, or the third memory area; and 
 a verification circuit configured to:
 compare an indication of a request for access to an associated memory area with the information data contained in a corresponding set of registers, and 
 authorize or prohibit access to the associated memory area based on the comparison. 
 
 
     
     
       19. The SoC circuit of  claim 18 , wherein contents of a register associated with the first memory area is modifiable based on a command from the second processing unit. 
     
     
       20. The SoC circuit of  claim 15 , further comprising:
 a memory management circuit coupled between the firewall device, the first processing unit, and the second processing unit, the memory management circuit configured to not degrade the security level of a secure level access request.