US12174440B2ActiveUtilityA1
Photonics package integration
Assignee: TAIWAN SEMICONDUCTOR MFG CO LTDPriority: Aug 15, 2018Filed: Jul 29, 2022Granted: Dec 24, 2024
Est. expiryAug 15, 2038(~12.1 yrs left)· nominal 20-yr term from priority
H10H 20/855G02B 6/424G02B 6/4204G02B 6/4246G02B 6/4214G02B 6/4249G02B 6/4257G02B 6/43G02B 6/421H01L 33/58
76
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Cited by
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Claims
Abstract
An interconnect package integrates a photonic die, an electronic die, and a switch ASIC into one package. At least some of the components in the electronic die, such as, for example, the serializer/deserializer circuits, transceivers, clocking circuitry, and/or control circuitry are integrated into the switch ASIC to produce an integrated switch ASIC. The photonic die is attached and electrically connected to the integrated switch ASIC.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. A device, comprising:
a first substrate;
a plurality of light sources; and
an interconnect package connected to the first substrate, the interconnect package comprising a photonics die (pDie) connected to an integrated switch Application Specific Integrated Circuit (ASIC) integrated into one package, wherein the pDie and the integrated switch ASIC are arranged in a diving-board configuration such that a portion of the pDie extends beyond an edge of the integrated switch ASIC, and wherein the pDie is disposed in a cutout formed in the first substrate; and
a plurality of optical elements disposed in a plurality of openings in the substrate and attached to the portion of the pDie that extends beyond the edge of the integrated switch ASIC, wherein each optical element of the plurality of optical elements is optically aligned with a respective light source of the plurality of light sources.
2. The device of claim 1 , wherein the integrated switch ASIC comprises one or more switches and one or more serializer/deserializer circuits positioned around a periphery of the integrated switch ASIC.
3. The device of claim 1 , wherein the integrated switch ASIC further comprises one or more transceivers positioned around a periphery of the integrated switch ASIC.
4. The device of claim 1 , wherein the integrated switch ASIC further comprises one or more clocking circuits.
5. The device of claim 1 , further comprising:
a second substrate attached to the first substrate; and
a waveguide formed in the second substrate and optically aligned with an optical element of the plurality of optical elements to optically couple the respective light source to the waveguide.
6. The device of claim 5 , wherein
the optical element is aligned with a first end of the waveguide; and
the interconnect package further comprises an optical interconnect optically coupled to a second end of the waveguide.
7. The device of claim 1 , wherein a heat spreader is positioned over the interconnect package and attached to the first substrate.
8. The device of claim 1 , further comprising an optical coupler attached to an exposed surface.
9. A method comprising:
attaching a photonics die (pDie) to an integrated switch Application Specific Integrated Circuit (ASIC) to produce an interconnect package;
attaching the interconnect package to a first substrate, wherein the pDie comprises a plurality of light sources and a plurality of detectors arranged in pairs of a light source and a detector, wherein the integrated switch ASIC and the pDie are arranged in a diving-board configuration such that a portion of the pDie extends beyond an edge of the integrated switch ASIC to provide an exposed surface, and wherein the pDie is disposed in a cutout formed in the first substrate; and
positioning an optical element in an opening of the first substrate and attached to the portion of the pDie that extends beyond the edge of the integrated switch ASIC, wherein the optical element is optically aligned with a light source on the pDie.
10. The method of claim 9 , wherein:
the opening in the first substrate comprises a first opening;
the optical element comprises a first optical element; and
the method further comprises positioning a second optical element at a second opening in the first substrate, wherein the second optical element is optically aligned with a respective detector on the pDie.
11. The method of claim 10 , wherein the method further comprises:
providing a first waveguide in a second substrate;
providing a second waveguide in the second substrate; and
attaching the second substrate to the first substrate, wherein the first waveguide is optically aligned with the first optical element and the second waveguide is optically aligned with the second optical element.
12. The method of claim 11 , further comprising optically coupling a first interconnect to the first waveguide and optical coupling a second interconnect to the second waveguide.
13. The method of claim 10 , further comprising positioning a heat spreader over the interconnect package and attaching the heat spreader to the substrate.
14. An interconnect package, comprising:
a first substrate;
a plurality of light sources;
an integrated switch Application Specific Integrated Circuit (ASIC) attached to the first substrate; and
a photonics die (pDie) attached and electrically connected to the integrated switch ASIC, the pDie comprising a plurality of detectors, wherein the pDie is disposed in a cutout formed in the first substrate, wherein the integrated switch ASIC and the pDie are arranged in a diving-board configuration such that a portion of the pDie extends beyond an edge of the integrated switch ASIC to provide an exposed surface, wherein the plurality of detectors and a plurality of light sources are arranged in pairs of a light source and a detector on the portion of the pDie that extends beyond the edge of the integrated switch ASIC, and wherein each of the plurality of light sources are optically aligned with an optical element disposed in an opening in the substrate.
15. The interconnect package of claim 14 , wherein the integrated switch ASIC comprises one or more switches and one or more serializer/deserializer circuits.
16. The interconnect package of claim 14 , wherein the integrated switch ASIC further comprises one or more transceivers.
17. The interconnect package of claim 14 , wherein the integrated switch ASIC further comprises one or more clocking circuits.
18. The interconnect package of claim 14 , further comprising:
an optical element positioned in an opening in the first substrate and optically aligned with a respective light source;
a second substrate attached to the first substrate; and
a waveguide formed in the second substrate and optically aligned with the optical element to optically couple the respective light source to the waveguide.
19. The interconnect package of claim 18 , wherein
the optical element is aligned with a first end of the waveguide; and
the interconnect package further comprises an optical interconnect optically coupled to a second end of the waveguide.
20. The interconnect package of claim 18 , wherein a heat spreader is positioned over the interconnect package and attached to one of the first substrate or the second substrate.Cited by (0)
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