US12174784B2ActiveUtilityA1

Method, apparatus, and computer-readable medium for parallelization of a computer program on a plurality of computing cores

86
Assignee: CORNAMI INCPriority: Sep 10, 2013Filed: Nov 9, 2023Granted: Dec 24, 2024
Est. expirySep 10, 2033(~7.2 yrs left)· nominal 20-yr term from priority
G06Q 40/00G06F 8/45G06F 15/8046
86
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Claims

Abstract

An apparatus, computer-readable medium, and computer-implemented method for parallelization of a computer program on a plurality of computing cores includes receiving a computer program comprising a plurality of commands, decomposing the plurality of commands into a plurality of node networks, each node network corresponding to a command in the plurality of commands and including one or more nodes corresponding to execution dependencies of the command, mapping the plurality of node networks to a plurality of systolic arrays, each systolic array comprising a plurality of cells and each non-data node in each node network being mapped to a cell in the plurality of cells, and mapping each cell in each systolic array to a computing core in the plurality of computing cores.

Claims

exact text as granted — not AI-modified
The invention claimed is: 
     
       1. A method executed by one or more computing devices for parallelization of a computer program on a plurality of computing cores, the method comprising:
 decomposing, by at least one of the one or more computing devices, a plurality of computer executable commands into a plurality of node networks; 
 mapping, by at least one of the one or more computing devices, the plurality of node networks to a plurality of systolic arrays, wherein each systolic array comprises a plurality of cells and wherein data nodes in each node network are mapped to a cell in the plurality of cells; and 
 mapping, by at least one of the one or more computing devices, each cell in each systolic array to a computing core in the plurality of computing cores. 
 
     
     
       2. An apparatus for parallelization of a computer program on a plurality of computing cores, the apparatus comprising:
 one or more processors; and one or more memories operatively coupled to at least one of the one or more processors and having instructions stored thereon that, when executed by at least one of the one or more processors, cause at least one of the one or more processors to:
 decompose a plurality of computer executable commands into a plurality of node networks; 
 map the plurality of node networks to a plurality of systolic arrays, wherein each systolic array comprises a plurality of cells and wherein data nodes in each node network are mapped to a cell in the plurality of cells; and 
 map each cell in each systolic array to a computing core in the plurality of computing cores. 
 
 
     
     
       3. At least one non-transitory computer-readable medium storing computer-readable instructions that, when executed by one or more computing devices, cause at least one of the one or more computing devices to:
 decompose a plurality of computer executable commands into a plurality of node networks; 
 map the plurality of node networks to a plurality of systolic arrays, wherein each systolic array comprises a plurality of cells and wherein data nodes in each node network are mapped to a cell in the plurality of cells; and 
 map each cell in each systolic array to a computing core in the plurality of computing cores.

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