Electrostatic discharge and electrical overstress detection circuit

Abstract

An electrostatic discharge and electrical overstress detection circuit includes protection circuit, sensing circuit, clamp circuit, several stages of sampling logic circuits connected in sequence and storage circuit. Protection circuit is coupled between input/output pin and internal chip and discharges to a power supply terminal when the electrostatic discharge or electrical overstress events happen. Sensing circuit and clamp circuit are coupled between power supply terminal and ground terminal. Each stage of sampling logic circuit is coupled to power supply terminal and memory cell of storage circuit, and the first stage of sampling logic is coupled to the clamp circuit, and when the electrostatic discharge or electrical overstress events happen, the several stages of sampling logic circuits sample voltage of the power supply terminal one by one and change state of corresponding memory cell, so that the electrostatic discharge or electrical overstress events are successively recorded by the memory cell.

What is claimed is: 
     
       1. An electrostatic discharge and electrical overstress detection circuit for recording electrostatic discharge and electrical overstress events on an input/output pin coupled with an internal chip, wherein the detection circuit comprises: a protection circuit, a sensing circuit, a clamp circuit, several stages of sampling logic circuits connected in sequence and a storage circuit, wherein the protection circuit is coupled between the input/output pin and the internal chip and discharges to a power supply terminal when the electrostatic discharge or electrical overstress events happen, the sensing circuit and the clamp circuit are coupled between the power supply terminal and a ground terminal, each stage of sampling logic circuit is coupled to the power supply terminal and a memory cell of the storage circuit, and the first stage of sampling logic circuit is coupled to the clamp circuit, and when the electrostatic discharge or electrical overstress events happen, the several stages of sampling logic circuits sample voltage of the power supply terminal one by one and change state of corresponding memory cell, so that the electrostatic discharge or electrical overstress events are successively recorded by the memory cells. 
     
     
       2. The electrostatic discharge and electrical overstress detection circuit according to  claim 1 , wherein the clamp circuit comprises a first inverter and an NMOS transistor, an input terminal of the first inverter is coupled to an output terminal of the sensing circuit, an output terminal of the first inverter is coupled to a gate of the NMOS transistor, a drain of the NMOS transistor is coupled to the power supply terminal, and a source of the NMOS transistor is coupled to the ground terminal. 
     
     
       3. The electrostatic discharge and electrical overstress detection circuit according to  claim 2 , wherein the first stage of sampling logic circuit in the several stages of sampling logic circuits comprises a second inverter and a PMOS transistor, and each of the other stages of sampling logic circuits in the several stages of sampling logic circuits comprise a NAND gate and a PMOS transistor, wherein an input terminal of the second inverter and a first input terminal of each NAND gate are coupled to an output terminal of the first inverter, an output terminal of the second inverter is coupled to a gate of the PMOS transistor of this stage, an output terminal of each NAND gate is coupled to the gate of the PMOS transistor of this stage, a source of each PMOS transistor is coupled to the power supply terminal, a drain of each PMOS transistor is coupled to a first terminal of the memory cell of this stage, and a second input terminal of each NAND gate is coupled to a third terminal of memory cell of upper stage. 
     
     
       4. The electrostatic discharge and electrical overstress detection circuit according to  claim 3 , wherein a second terminal of the memory cell is coupled to the power supply terminal; and when an electrostatic discharge or electrical overstress event happens on the input/output pin, the drain of the PMOS transistor is conductive with the second input terminal of the NAND gate of next stage. 
     
     
       5. The electrostatic discharge and electrical overstress detection circuit according to  claim 4 , wherein the memory cell is an anti-fuse memory cell, and when the electrostatic discharge or electrical overstress event happens on the input/output pin, a gate oxide layer of the anti-fuse memory cell is broken down, and the drain of the PMOS transistor is conductive with the second input terminal of the NAND gate of next stage. 
     
     
       6. The electrostatic discharge and electrical overstress detection circuit according to  claim 4 , wherein the memory cell is a flash memory cell, a magnetic random memory cell or a resistance-variable random memory cell, and when the electrostatic discharge and electrical overstress event happens on the input/output pin, the memory cell is erased, and the drain of the PMOS transistor is conductive with the second input terminal of the NAND gate of next stage. 
     
     
       7. The electrostatic discharge and electrical overstress detection circuit according to  claim 2 , wherein the first stage of sampling logic circuit in the several stages of sampling logic circuits comprises a second inverter and a PMOS transistor, and each of the other stages of sampling logics in the several stages of sampling logic circuits comprises a NAND gate and a PMOS transistor, wherein an input terminal of the second inverter and a first input terminal of each NAND gate are coupled to an output terminal of the first inverter, an output terminal of the second inverter is coupled to a gate of the PMOS transistor of this stage, an output terminal of each NAND gate is coupled to the gate of the PMOS transistor of this stage, a source of each PMOS transistor is coupled to the power supply terminal, a drain of each PMOS transistor is coupled to one terminal of corresponding memory cell and a second input terminal of the NAND gate of next stage; and the other terminal of the memory cell is coupled to the ground terminal. 
     
     
       8. The electrostatic discharge and electrical overstress detection circuit according to  claim 6 , wherein the memory cell is a one-time programmable memory cell, and when the electrostatic discharge and electrical overstress event happens on the input/output pin, the one-time programmable memory cell is disconnected, and the drain of the PMOS transistor is conductive with the second input terminal of the NAND gate of next stage. 
     
     
       9. The electrostatic discharge and electrical overstress detection circuit according to  claim 1 , further comprising a readout circuit coupled to the storage circuit and is used to read out state of each memory cell for analyzing numbers and stages of occurrence of the electrostatic discharge and electrical overstress events. 
     
     
       10. The electrostatic discharge and electrical overstress detection circuit according to  claim 1 , wherein when an electrostatic discharge and electrical overstress event happens on the input/output pin, one memory cell of the storage circuit is switched from a first state to a second state. 
     
     
       11. The electrostatic discharge and electrical overstress detection circuit according to  claim 1 , wherein the protection circuit comprises a first-level protection unit and a second-level protection unit, each of the first-level protection unit and the second-level protection unit comprises a first diode and a second diode, an anode of the first diode is coupled to the input/output pin, and a cathode of the first diode is coupled to the power supply terminal, an anode of the second diode is coupled to the ground terminal, a cathode of the second diode is coupled to the input/output pin, wherein a resistor is coupled between the first-level protection unit and the second-level protection unit, and one terminal of the resistor is coupled to the input/output pin and a node between the first diode and the second diode in the first-level protection unit, the other terminal of the resistor is coupled to the internal chip and a node between the first diode and the second diode in the second-level protection unit.