US12199220B2ActiveUtilityA1
μ-LED, μ-LED device, display and method for the same
Assignee: OSRAM OPTO SEMICONDUCTORS GMBHPriority: Jan 29, 2019Filed: Dec 22, 2021Granted: Jan 14, 2025
Est. expiryJan 29, 2039(~12.6 yrs left)· nominal 20-yr term from priority
Inventors:Andreas BiebersdorfStefan IllekInes PietzonkaPetrus SundgrenChristoph KlempFelix FeixChristian BergerAna Kanevce
H10W 90/00B60K 35/235B60K 35/22H10H 20/8512H10H 20/856H10H 20/811B60K 2360/1523H10H 20/857H10H 20/872H10H 20/8514H10H 20/8513H10H 20/84H10H 20/825H10H 20/835H10H 20/819H10H 20/821H10H 20/818H10H 20/018H10H 29/14B60K 2360/332H10H 20/852B60K 35/00H01L 33/60H01L 33/502H01L 33/04H01L 25/0753H01L 33/52
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Claims
Abstract
The invention relates to various aspects of a μ-LED or a μ-LED array for augmented reality or lighting applications, in particular in the automotive field. The μ-LED is characterized by particularly small dimensions in the range of a few μm.
Claims
exact text as granted — not AI-modifiedThe invention claimed is:
1. A method of producing an optoelectronic component including a μ-LED, comprising:
providing a semiconductor structure based on a phosphide material system comprising a first n-doped layer, a second p-doped layer, and an active layer with at least one quantum well disposed therebetween, wherein the p-doped layer comprises a first dopant;
applying a patterned mask on the semiconductor structure;
providing a second dopant;
diffusing, using first process parameters and during a first time period and at a first temperature, the second dopant into the p-doped layer in areas of the active layer over which no area of the patterned mask is located, such that quantum well intermixing is generated in the areas; and
annealing with second process parameters different from the first process parameters, at a second temperature higher than the first temperature during a subsequent second time period, without further addition of the second dopant, wherein the step of annealing comprises:
providing a phosphide precursor during the second time period and at the second temperature.
2. The method according to claim 1 , wherein the second dopant comprises Zn and comprises the same doping type as the first dopant.
3. The method according to claim 1 , wherein the second process parameters comprise a temperature greater than the first temperature of the first process parameters.
4. The method according to claim 1 , wherein the first and/or second process parameters are selected from at least one element of the group consisting of:
temperature;
temperature change over a defined period;
pressure;
pressure change over a defined period of time;
composition of a gas;
duration; and
a combination of the above,
wherein the first process parameters differ from the second process parameters in at least one parameter other than the duration.
5. The method according to claim 1 , wherein the mask is formed locally from a suitable layer of the semiconductor structure by a patterning step.
6. The method according to claim 1 , wherein the annealing further comprises adding a precursor comprising an element including P or As.
7. The method according to claim 1 , wherein the second dopant comprises Zn or Mg.
8. The method according to claim 1 , wherein the semiconductor structure comprises a III-V semiconductor material having at least one of the following material systems:
InP;
GaP;
InGaP;
InAlP;
GaAlP; and
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