Semiconductor memory device and a method of manufacturing the same

Abstract

A semiconductor memory device includes a device isolation pattern on a substrate to define an active region, a word line in the substrate, to intersect the active region, a first dopant region in the active region as at a first side of the word line, a second dopant region in the active region at a second side of the word line, a bit line connected to the first dopant region and intersecting the word line, a bit line contact connecting the bit line to the first dopant region, a landing pad on the second dopant region, and a storage node contact connecting the landing pad to the second dopant region, the storage node contact including a first portion in contact with the second dopant region, the first portion including a single-crystal silicon, and a second portion on the first portion and including a poly-silicon.

What is claimed is: 
     
       1. A method of manufacturing a semiconductor memory device, the method comprising:
 preparing a substrate including an active region and a device isolation pattern; 
 forming a word line buried in the substrate and crossing the active region of the substrate in a first direction that is parallel to a top surface of the substrate; 
 forming a bit line structure on the substrate, the bit line structure including a bit line contact disposed on the active region of the substrate, and a bit line disposed on the bit line contact and crossing the active region of the substrate in a second direction that is parallel to the top surface of the substrate and that is perpendicular to the first direction; 
 forming a spacer on a sidewall of the bit line structure; 
 exposing a portion of a top surface of the active region of the substrate using the spacer as a mask; and 
 forming a storage node contact covering the spacer, 
 wherein forming the storage node contact includes: 
 forming a first portion of a single-crystal phase on the portion of the top surface of the active region of the substrate by a selective epitaxial growth process; 
 forming a second portion of an amorphous phase on the first portion, the second portion including a void; and 
 performing a thermal treatment process on the second portion to remove the void of the second portion, and 
 wherein the amorphous phase of the second portion of the storage node contact is changed into a poly-crystal phase or a single-crystal phase by the thermal treatment process. 
 
     
     
       2. The method as claimed in  claim 1 , wherein:
 the first portion of the storage node contact includes single-crystal silicon, and 
 after performing the thermal treatment process, the second portion of the storage node contact includes poly-silicon or single-crystal silicon. 
 
     
     
       3. The method as claimed in  claim 1 , wherein:
 exposing the portion of the top surface of the active region of the substrate includes removing a part of the active region of the substrate, and 
 the first portion of the storage node contact is disposed in a region in which the part of the active region of the substrate is removed. 
 
     
     
       4. The method as claimed in  claim 1 , wherein an interface of the first portion and the second portion of the storage node contact is disposed at a higher level than a bottom surface of the bit line contact of the bit line structure, and disposed at a lower level than a top surface of the bit line contact of the bit line structure. 
     
     
       5. The method as claimed in  claim 1 , wherein an interface of the first portion and the second portion of the storage node contact is disposed at same level with a top surface of the bit line contact of the bit line structure. 
     
     
       6. The method as claimed in  claim 1 , further comprising forming an interlayer insulating pattern on the substrate,
 wherein a part of the interlayer insulating pattern is removed during exposing of the portion of the top surface of the active region of the substrate, and 
 wherein a lower part of the first portion of the storage node contact is disposed under the interlayer insulating pattern. 
 
     
     
       7. The method as claimed in  claim 1 , further comprising forming an interlayer insulating pattern on the substrate,
 wherein the bit line contact of the bit line structure penetrates the interlayer insulating pattern and contacts the active region of the substrate, and 
 wherein the storage node contact penetrates the interlayer insulating pattern and contacts the active region of the substrate. 
 
     
     
       8. The method as claimed in  claim 7 , wherein:
 the first portion of the storage node contact includes a first side surface that faces the bit line contact of the bit line structure, 
 the second portion of the storage node contact includes a second side surface that faces the bit line contact of the bit line structure, and 
 a distance between the first side surface of the first portion of the storage node contact and the bit line contact of the bit line structure in the first direction is greater than a distance between the second side surface of the second portion of the storage node contact and the bit line contact of the bit line structure in the first direction. 
 
     
     
       9. The method as claimed in  claim 7 , wherein:
 a lower part of the first portion of the storage node contact includes a first side surface that faces the bit line contact of the bit line structure, 
 an upper part of first portion of the storage node contact includes a second side surface that faces the bit line contact of the bit line structure, and 
 a distance between the first side surface of the lower part of the first portion of the storage node contact and the bit line contact of the bit line structure in the first direction is greater than a distance between the second side surface of the upper part of the first portion of the storage node contact and the bit line contact of the bit line structure in the first direction. 
 
     
     
       10. The method as claimed in  claim 9 , wherein:
 the lower part of the first portion of the storage node contact is in contact with the active region and the device isolation pattern of the substrate, and 
 the upper part of the first portion of the storage node contact is in contact with the interlayer insulating pattern and the spacer. 
 
     
     
       11. A method of manufacturing a semiconductor memory device, the method comprising:
 preparing a substrate including an active region and a device isolation pattern; 
 forming a word line buried in the substrate and crossing the active region of the substrate in a first direction that is parallel to a top surface of the substrate; 
 forming a bit line structure on the substrate, the bit line structure including a bit line contact disposed on the active region of the substrate, and a bit line disposed on the bit line contact and crossing the active region of the substrate in a second direction that is parallel to the top surface of the substrate and that is perpendicular to the first direction; 
 forming a spacer on a sidewall of the bit line structure; 
 exposing a portion of a top surface of the active region of the substrate using the spacer as a mask; and 
 forming a storage node contact covering the spacer, 
 wherein forming the storage node contact includes: 
 forming a first portion on the portion of the top surface of the active region of the substrate by a selective epitaxial growth process; 
 forming a second portion on the first portion, the second portion including a void; and 
 performing a thermal treatment process on the second portion to remove the void of the second portion, 
 wherein a crystallinity of the first portion of the storage node contact is different from a crystallinity of the second portion of the storage node contact, and 
 wherein an interface of the first portion and the second portion of the storage node contact is at a level between a bottom surface and a top surface of the bit line contact. 
 
     
     
       12. The method as claimed in  claim 11 , wherein the crystallinity of the first portion of the storage node contact is higher than the crystallinity of the second portion of the storage node contact. 
     
     
       13. The method as claimed in  claim 11 , wherein, before performing the thermal treatment process:
 the first portion of the storage node contact includes a single-crystal phase, and 
 the second portion of the storage node contact includes an amorphous phase. 
 
     
     
       14. The method as claimed in  claim 11 , wherein:
 the first portion of the storage node contact includes single-crystal silicon, and 
 after performing the thermal treatment process, the second portion of the storage node contact includes poly-silicon or single-crystal silicon. 
 
     
     
       15. The method as claimed in  claim 11 , wherein, after performing the thermal treatment process, the amorphous phase of the second portion of the storage node contact is changed into a poly-crystal phase or a single-crystal phase by the thermal treatment process. 
     
     
       16. The method as claimed in  claim 11 , wherein:
 exposing the portion of the top surface of the active region of the substrate includes removing a part of the active region, and 
 the first portion of the storage node contact is disposed in a region in which the part of the active region of the substrate is removed. 
 
     
     
       17. The method as claimed in  claim 11 , further comprising forming an interlayer insulating pattern on the substrate, wherein:
 a part of the interlayer insulating pattern is removed during exposing of the portion of the top surface of the active region of the substrate, 
 the first portion of the storage node contact includes a lower part and an upper part that is disposed on the lower part, 
 the lower part of the first portion of the storage node contact penetrates the interlayer insulating pattern and is in contact with the active region and the device isolation pattern of the substrate, and 
 the upper part of the first portion of the storage node contact is in contact with the interlayer insulating pattern and the spacer. 
 
     
     
       18. The method as claimed in  claim 11 , further comprising forming an interlayer insulating pattern on the substrate, wherein:
 the first portion of the storage node contact includes a lower part and an upper part that is disposed on the lower part, 
 the lower part of the first portion of the storage node contact includes a first side surface that faces the bit line contact of the bit line structure, 
 the upper part of the first portion of the storage node contact includes a second side surface that faces the bit line contact of the bit line structure, and 
 a distance between the first side surface of the lower part of the first portion of the storage node contact and the bit line contact of the bit line structure in the first direction is greater than a distance between the second side surface of the upper part of the first portion of the storage node contact and the bit line contact of the bit line structure in the first direction. 
 
     
     
       19. The method as claimed in  claim 11 , wherein:
 the first portion of the storage node contact includes a first side surface that faces the bit line contact of the bit line structure, 
 the second portion of the storage node contact includes a second side surface that faces the bit line contact of the bit line structure, and 
 a distance between the first side surface of the first portion of the storage node contact and the bit line contact of the bit line structure in the first direction is greater than a distance between the second side surface of the second portion of the storage node contact and the bit line contact of the bit line structure in the first direction. 
 
     
     
       20. A method of manufacturing a semiconductor memory device, the method comprising:
 preparing a substrate including an active region and a device isolation pattern; 
 forming a word line buried in the substrate and crossing the active region of the substrate in a first direction that is parallel to a top surface of the substrate; 
 forming an interlayer insulating pattern on the substrate; 
 forming a bit line structure on the substrate, the bit line structure including a bit line contact disposed on the active region of the substrate, and a bit line disposed on the bit line contact and crossing the active region of the substrate in a second direction that is parallel to the top surface of the substrate and that is perpendicular to the first direction; 
 forming a spacer on a sidewall of the bit line structure; 
 exposing a portion of a top surface of the active region of the substrate by removing a part of the interlayer insulating pattern; 
 forming a first portion of a storage node contact on the portion of the top surface of the active region of the substrate by a selective epitaxial growth process; 
 forming a second portion of the storage node contact on the first portion of the storage node contact; and 
 performing a thermal treatment process on the second portion of the storage node contact, 
 wherein: 
 the first portion of the storage node contact includes single-crystal silicon, 
 the second portion of the storage node contact includes poly-silicon or single-crystal silicon, 
 the first portion of the storage node contact includes a lower part and an upper part that is disposed on the lower part, 
 the lower part of the first portion of the storage node contact is in contact with the active region and the device isolation pattern of the substrate, 
 the upper part of the first portion of the storage node contact is in contact with the interlayer insulating pattern and the spacer, 
 the lower part of the first portion of the storage node contact includes a first side surface that faces the bit line contact of the bit line structure, 
 the upper part of the first portion of the storage node contact includes a second side surface that faces the bit line contact of the bit line structure, 
 the second portion of the storage node contact includes a third side surface that faces the bit line contact of the bit line structure, 
 a distance between the first side surface of the lower part of the first portion of the storage node contact and the bit line contact of the bit line structure in the first direction is greater than a distance between the second side surface of the upper part of the first portion of the storage node contact and the bit line contact of the bit line structure in the first direction, and 
 the distance between the second side surface of the upper part of the first portion of the storage node contact and the bit line contact of the bit line structure in the first direction is greater than a distance between the third side surface of the second portion of the storage node contact and the bit line contact of the bit line structure.