Inserting predefined pad values into a stream of vectors

Abstract

Software instructions are executed on a processor within a computer system to configure a streaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array and a pad value indicator. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. A padded stream vector is formed that includes a specified pad value without accessing the pad value from system memory.

The invention claimed is: 
     
       1. A device comprising:
 a processor core; 
 a memory; 
 a register configured to store a template that specifies, for a set of data:
 a data width of the set of data along a first dimension; 
 an amount of data to retrieve from the memory to form a first portion of the set of data in the first dimension; and 
 a pad value to use for a second portion of the set of data in the first dimension; and 
 
 a stream circuit coupled between the processor core and configured to, based on a stream open instruction that is associated with the template:
 generate the set of data by:
 retrieving data of the first portion from the memory; and 
 generating the second portion of the set of data based on the pad value without accessing the memory; and 
 
 provide the set of data to the processor core. 
 
 
     
     
       2. The device of  claim 1 , wherein the template includes a field that specifies whether the pad value is a minimum representable value or a maximum representable value. 
     
     
       3. The device of  claim 1 , wherein the template includes a field that specifies whether the pad value is an unsigned minimum representable value, an unsigned maximum representable value, a signed minimum representable value, or a signed maximum representable value. 
     
     
       4. The device of  claim 1 , wherein the template specifies the amount of data to retrieve in the first dimension by specifying a count of iterations of a loop in the first dimension. 
     
     
       5. The device of  claim 1 , wherein the template specifies the amount of data to retrieve in the first dimension by specifying a number of data elements to retrieve and a size of each of the data elements. 
     
     
       6. The device of  claim 1 , wherein the template specifies the first dimension from among a plurality of dimensions of the set of data. 
     
     
       7. The device of  claim 1 , wherein the stream circuit includes an alignment circuit that includes:
 a register configured to store the data of the first portion of the set of data; 
 a set of multiplexers coupled to the register; and 
 control logic coupled to the set of multiplexers and configured to cause the set of multiplexers to generate the set of data by providing the data of the first portion from the register and generating the second portion of the set of data based on the pad value. 
 
     
     
       8. The device of  claim 7 , wherein the stream circuit includes:
 a memory interface coupled to the memory and configured to retrieve the data of the first portion of the set of data; and 
 a butterfly network coupled between the memory interface and the register and configured to reorder the data of the first portion of the set of data prior to the storing of the data of the first portion in the register. 
 
     
     
       9. The device of  claim 1 , wherein:
 the stream circuit includes an address generator configured to generate a set of addresses based on the template; and 
 the stream circuit is configured to retrieve the data of the first portion from the memory using the set of addresses. 
 
     
     
       10. The device of  claim 1 , wherein the memory is a level-two (L2) cache memory. 
     
     
       11. The device of  claim 10  further comprising a level-one (L1) cache memory coupled between the processor core and the L2 cache memory, wherein the stream circuit is coupled between the processor core and the L2 cache memory in parallel with the L1 cache memory. 
     
     
       12. A method comprising:
 receiving, by a circuit device, a stream instruction; and 
 based on the stream instruction:
 receiving, from a register, a template that specifies, for a set of data:
 a width of the set of data along a first dimension; 
 a subset of the set of data to retrieve from a memory for a first portion of the set of data in the first dimension; and 
 a pad value for a second portion of the set of data in the first dimension; 
 
 retrieving, from the memory, the subset of the set of data; 
 generating the second portion of the set of data based on the pad value without accessing the memory; and 
 providing the set of data to a processing circuit. 
 
 
     
     
       13. The method of  claim 12 , wherein the template includes a field that specifies whether the pad value is a minimum representable value or a maximum representable value. 
     
     
       14. The method of  claim 13 , wherein the field specifies whether the pad value is signed or unsigned. 
     
     
       15. The method of  claim 12 , wherein the template specifies the subset of the set of data to retrieve from the memory by specifying a count of iterations of a loop in the first dimension. 
     
     
       16. The method of  claim 12 , wherein the template specifies the subset of the set of data to retrieve from the memory by specifying a number of data elements to retrieve and a size of each of the data elements. 
     
     
       17. The method of  claim 12 , wherein the template specifies the first dimension from among a plurality of dimensions of the set of data. 
     
     
       18. The method of  claim 12  further comprising reordering the subset of the set of data prior to the providing of the set of data. 
     
     
       19. The method of  claim 12 , wherein the memory is a level-two (L2) cache memory. 
     
     
       20. The method of  claim 12 , wherein the stream instruction specifies the template by specifying the register from among a set of registers.