Testing of analog neural memory cells in an artificial neural network

Abstract

In one example, a method of testing a plurality of non-volatile memory cells in an array of non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, comprises asserting, by the row decoder, all word lines in the array; asserting, by the column decoder, all bit lines in the array; performing a deep programming operation on the array of non-volatile memory cells; and measuring a total current received from the bit lines.

What is claimed is: 
     
       1. A method of testing a plurality of non-volatile memory cells in an array of non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising:
 asserting, by the row decoder, all word lines in the array and at the same time asserting, by the column decoder, all bit lines in the array; 
 performing a deep programming operation on the array of non-volatile memory cells; 
 measuring a total current received from the bit lines; and 
 identifying a die containing the array as bad if the total current received from the bit lines is lower than a threshold value. 
 
     
     
       2. The method of  claim 1 , wherein the non-volatile memory cells are stacked-gate flash memory cells. 
     
     
       3. The method of  claim 1 , wherein the non-volatile memory cells are split-gate flash memory cells. 
     
     
       4. The method of  claim 1 , wherein the array is part of a neural network. 
     
     
       5. A system comprising:
 an array of non-volatile memory cells, wherein the non-volatile memory cells are arranged in rows and columns and the rows are coupled to respective word lines and the columns are coupled to respective bit lines; and 
 test control logic to perform an algorithm comprising:
 asserting all word lines in the array and at the same time asserting all bit lines in the array; 
 performing a deep programming operation on the non-volatile memory cells; and 
 measuring a total current received from the bit lines; and 
 identifying a die containing the array as bad if the total current received from the bit lines is lower than a threshold value. 
 
 
     
     
       6. The system of  claim 5 , wherein the non-volatile memory cells are stacked-gate flash memory cells. 
     
     
       7. The system of  claim 5 , wherein the non-volatile memory cells are split-gate flash memory cells. 
     
     
       8. The system of  claim 5 , wherein the array is part of a neural network.