Radar system

Abstract

Radar System The disclosure relates to a radar system having multiple radar transceiver modules, in which each module has a clock signal that is synchronised with a clock signal generated by a leader transceiver module. Example embodiments include a radar system (400) comprising a plurality of radar transceiver modules (401, 402) mounted to a common PCB (404), the plurality of radar transceiver modules comprising a leader module (401) and one or more follower modules (402), the leader module (401) comprising a first oscillator (403) configured to provide a first clock signal at a first frequency to each follower module (402), each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator (300), the PLL clock signal generator (300) comprising a divide by n clock divider (304) arranged to output 2n phase shifted clock signals (314) at a third frequency and a multiplexer (306) connected to receive the 2n phase shifted clock signals from the divide by n clock divider (304) and output a third clock signal (308) selected by an input phase select signal (307).

What is claimed is: 
     
       1. A radar system comprising a plurality of radar transceiver modules mounted to a common PCB, the plurality of radar transceiver modules comprising a leader module and one or more follower modules, the leader module comprising a first oscillator configured to provide a first clock signal at a first frequency to each follower module, each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator comprising:
 a phase comparator connected to receive the first clock signal and a feedback signal; 
 a loop filter connected to receive an output signal from the phase comparator; 
 a second oscillator connected to receive an output signal from the loop filter and generate a second clock signal at a second frequency; 
 a divide by n clock divider connected to receive the second clock signal from the second oscillator and to output 2n phase shifted clock signals at a third frequency; 
 a feedback device connected to receive one of the phase shifted clock signals from the divide by n clock divider and provide the feedback signal to the phase comparator; and 
 a multiplexer connected to receive the 2n phase shifted clock signals from the divide by n clock divider and output a third clock signal selected by an input phase select signal; 
 wherein the divide-by-n clock divider in each of the plurality of radar transceiver modules comprises a divider core configured to divide the second clock signal into an intermediate clock signal, a chain of flip-flops configured to receive alternating edges of the intermediate clock signal and a plurality of logic gates arranged to combine outputs from consecutive pairs of the chain of flip-flops to provide the output phase shifted clock signals at the third frequency, and 
 wherein the divide by n clock divider comprises five flip-flops, FFs, arranged to receive the second clock signal from the second oscillator, three OR gates and one AND gate arranged to receive outputs from the FFs. 
 
     
     
       2. The radar system of  claim 1 , wherein the output of the multiplexer in each of the plurality of radar transceiver modules is connected to an analog to digital converter, ADC, arranged to receive signals from a radar signal receiver. 
     
     
       3. The radar system of  claim 1 , wherein n is an odd integer of 3 or more. 
     
     
       4. The radar system of  claim 3 , wherein n=3, 5 or 7. 
     
     
       5. The radar system of  claim 1  wherein the divide by n clock divider comprises three inverters connected to a respective OR gate output, 3 of the phase shifted clock signals being output by the OR gates and another 3 of the phase shifted clock signals being output by the inverters. 
     
     
       6. The radar system of  claim 1 , wherein the divide by n clock divider comprises eight FFs arranged to receive the second clock signal from the second oscillator and six OR gates arranged to receive outputs from the FFs and provide the 2n phase shifted clock signals. 
     
     
       7. The radar system of  claim 1 , wherein the divide by n clock divider comprises five FFs arranged to receive the second clock signal from the second oscillator, three OR gates arranged to receive outputs from the FFs and provide n of the 2n phase shifted clock signals and three AND gates arranged to receive outputs from the FFs and provide another n of the 2n phase shifted clock signals. 
     
     
       8. The radar system of  claim 1 , wherein the first frequency is in a range of between around 1 and 100 MHz. 
     
     
       9. The radar system of  claim 1 , wherein the third frequency is in a range between around 1 and 10 GHz. 
     
     
       10. The radar system of  claim 1 , comprising a non-volatile memory configured to store a value of the input phase select signal, the radar system being configured to retrieve a stored value of the input phase select signal for each module during operation of the radar system. 
     
     
       11. The radar system of  claim 1 , wherein the feedback device in each of the plurality of radar transceiver modules is a divide-by-m clock divider and/or a time-to-digital converter. 
     
     
       12. A method of calibrating a radar system according to  claim 1 , the method comprising:
 operating each of the plurality of radar transceiver modules to detect a target; 
 determine a phase select signal for the divide by n clock divider of the PLL clock signal generator in each module to minimize a difference in phase between the third clock signal in each follower module and in the leader module; and 
 storing the determined phase select signal for each of the plurality of radar transceiver modules in a non-volatile memory. 
 
     
     
       13. A method of operating a radar system according to  claim 1 , the method comprising:
 retrieving a phase select signal for each of the plurality of radar transceiver modules from a non-volatile memory; and 
 operating each of the plurality of radar transceiver modules while providing the retrieved phase select signal to the divide by n clock divider of the PLL clock signal generator in each module. 
 
     
     
       14. The method of  claim 13 , wherein the divide-by-n clock divider in each of the plurality of radar transceiver modules comprises a divider core configured to divide the second clock signal into an intermediate clock signal, a chain of flip-flops configured to receive alternating edges of the intermediate clock signal and a plurality of logic gates arranged to combine outputs from consecutive pairs of the chain of flip-flops to provide the output phase shifted clock signals at the third frequency. 
     
     
       15. The method of  claim 13 , wherein the output of the multiplexer in each of the plurality of radar transceiver modules is connected to an analog to digital converter, ADC, arranged to receive signals from a radar signal receiver. 
     
     
       16. The method of  claim 13 , wherein the radar system comprises a non-volatile memory configured to store a value of the input phase select signal, the radar system being configured to retrieve a stored value of the input phase select signal for each module during operation of the radar system. 
     
     
       17. The method of  claim 13 , wherein the feedback device in each of the plurality of radar transceiver modules is a divide-by-m clock divider and/or a time-to-digital converter. 
     
     
       18. The method of  claim 13 , wherein the first frequency is in a range of between around 1 and 100 MHz. 
     
     
       19. A radar system comprising a plurality of radar transceiver modules mounted to a common PCB, the plurality of radar transceiver modules comprising a leader module and one or more follower modules, the leader module comprising a first oscillator configured to provide a first clock signal at a first frequency to each follower module, each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator comprising:
 a phase comparator connected to receive the first clock signal and a feedback signal; 
 a loop filter connected to receive an output signal from the phase comparator; 
 a second oscillator connected to receive an output signal from the loop filter and generate a second clock signal at a second frequency; 
 a divide by n clock divider connected to receive the second clock signal from the second oscillator and to output 2n phase shifted clock signals at a third frequency; 
 a feedback device connected to receive one of the phase shifted clock signals from the divide by n clock divider and provide the feedback signal to the phase comparator; and 
 a multiplexer connected to receive the 2n phase shifted clock signals from the divide by n clock divider and output a third clock signal selected by an input phase select signal; 
 wherein the divide-by-n clock divider in each of the plurality of radar transceiver modules comprises a divider core configured to divide the second clock signal into an intermediate clock signal, a chain of flip-flops configured to receive alternating edges of the intermediate clock signal and a plurality of logic gates arranged to combine outputs from consecutive pairs of the chain of flip-flops to provide the output phase shifted clock signals at the third frequency, and 
 wherein the divide by n clock divider comprises eight FFs arranged to receive the second clock signal from the second oscillator and six OR gates arranged to receive outputs from the FFs and provide the 2n phase shifted clock signals. 
 
     
     
       20. A radar system comprising a plurality of radar transceiver modules mounted to a common PCB, the plurality of radar transceiver modules comprising a leader module and one or more follower modules, the leader module comprising a first oscillator configured to provide a first clock signal at a first frequency to each follower module, each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator comprising:
 a phase comparator connected to receive the first clock signal and a feedback signal; 
 a loop filter connected to receive an output signal from the phase comparator; 
 a second oscillator connected to receive an output signal from the loop filter and generate a second clock signal at a second frequency; 
 a divide by n clock divider connected to receive the second clock signal from the second oscillator and to output 2n phase shifted clock signals at a third frequency; 
 a feedback device connected to receive one of the phase shifted clock signals from the divide by n clock divider and provide the feedback signal to the phase comparator; and 
 a multiplexer connected to receive the 2n phase shifted clock signals from the divide by n clock divider and output a third clock signal selected by an input phase select signal; 
 wherein the divide-by-n clock divider in each of the plurality of radar transceiver modules comprises a divider core configured to divide the second clock signal into an intermediate clock signal, a chain of flip-flops configured to receive alternating edges of the intermediate clock signal and a plurality of logic gates arranged to combine outputs from consecutive pairs of the chain of flip-flops to provide the output phase shifted clock signals at the third frequency, and 
 wherein the divide by n clock divider comprises five FFs arranged to receive the second clock signal from the second oscillator, three OR gates arranged to receive outputs from the FFs and provide n of the 2n phase shifted clock signals and three AND gates arranged to receive outputs from the FFs and provide another n of the 2n phase shifted clock signals.