US12230695B2ActiveUtilityA1

Display substrate and manufacturing method thereof, display device

76
Assignee: BOE TECHNOLOGY GROUP CO LTDPriority: Nov 24, 2020Filed: Jun 21, 2023Granted: Feb 18, 2025
Est. expiryNov 24, 2040(~14.4 yrs left)· nominal 20-yr term from priority
Inventors:Meng Zhao
H10D 84/01H10D 30/6734H10D 86/471H10D 86/423H10D 86/0221H10D 86/60H10D 30/6755Y02P70/50H10D 99/00H10D 86/021H01L 29/7869H01L 29/78648H01L 27/127H01L 27/1251H01L 27/1225H01L 29/66969
76
PatentIndex Score
0
Cited by
13
References
18
Claims

Abstract

The present disclosure provides a display substrate and a manufacturing method thereof, and a display device, belongs to the field of display technology. The method includes forming a first thin film transistor, which includes: forming a first gate of the first thin film transistor on a base substrate through a patterning process; forming a first gate insulating layer on a side of the first gate distal to the base substrate; sequentially forming a first semiconductor material layer, a second gate insulating layer and a second gate metal layer on a side of the first gate insulating layer distal to the base substrate, and forming a pattern including an active layer of the first thin film transistor, a pattern of the second gate insulating layer and a second gate of the first thin film transistor through a patterning process.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A display substrate, comprising a base substrate and a first thin film transistor on the substrate; wherein
 the first thin film transistor comprises a first gate on the base substrate, and a first gate insulating layer on a side of the first gate distal to the base substrate; 
 an active layer of the first thin film transistor is on a side of the first gate insulating layer distal to the base substrate; a second gate insulating layer is on a side of the active layer of the first thin film transistor distal to the base substrate; 
 a second gate of the first thin film transistor is on a side of the second gate insulating layer distal to the base substrate, and an orthographic projection of the second gate of the first thin film transistor on the base substrate is in an orthographic projection of the active layer of the first thin film transistor on the base substrate; a first interlayer insulating layer is on a side of the second gate of the first thin film transistor distal to the base substrate; 
 a source, a drain of the first thin film transistor and a gate line are on a side of the first interlayer insulating layer distal to the base substrate, and the source and the drain of the first thin film transistor are respectively connected to the active layer of the first thin film transistor through a source contact via and a drain contact via penetrating through the first interlayer insulating layer; the gate line is electrically connected to the second gate of the first thin film transistor through a first connection via penetrating through the first interlayer insulating layer; and 
 the gate line is electrically connected to the first gate of the first thin film transistor to receive a gate signal through a second connection via penetrating through the first interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer. 
 
     
     
       2. A display device, comprising the display substrate of  claim 1 . 
     
     
       3. The display substrate of  claim 1 , wherein a material of the active layer of the first thin film transistor comprises oxide semiconductor. 
     
     
       4. The display substrate of  claim 3 , further comprising a low temperature polycrystalline silicon thin film transistor on the base substrate,
 wherein the low temperature polycrystalline silicon thin film transistor comprises a third gate; and 
 the third gate, the first gate and the second gate are sequentially arranged in a direction away from the base substrate. 
 
     
     
       5. The display substrate of  claim 1 , wherein a depth of the first connection via is smaller than a depth of the source contact via and the drain contact via. 
     
     
       6. The display substrate of  claim 5 , wherein a depth of the second connection via is larger than the depth of the source contact via and the drain contact via. 
     
     
       7. The display substrate of  claim 5 , wherein the source contact via, a channel region of the active layer, and the drain contact via are arranged along a first direction;
 the first connection via and the second connection via are arranged along a second direction; and 
 the first direction crosses the second direction. 
 
     
     
       8. The display substrate of  claim 7 , wherein an area of an orthographic projection of the second gate on the base substrate is smaller than that of the active layer. 
     
     
       9. The display substrate of  claim 7 , wherein the gate line comprises a first part which is a strip extending along the second direction. 
     
     
       10. A method for manufacturing a display substrate, comprising: a step of forming a first thin film transistor; wherein the step of forming the first thin film transistor comprises steps of:
 forming a first gate of the first thin film transistor on a base substrate through a patterning process; 
 forming a first gate insulating layer on a side of the first gate distal to the base substrate; 
 sequentially forming a first semiconductor material layer, a second gate insulating material layer and a second gate metal layer on a side of the first gate insulating layer distal to the base substrate, and forming a pattern comprising an active layer of the first thin film transistor and a pattern comprising a second gate insulating layer and a second gate of the first thin film transistor; 
 forming a first interlayer insulating layer on a side of a layer, where the second gate of the first thin film transistor is located, distal to the base substrate, and forming a source contact via, a drain contact via and a first connection via penetrating through the first interlayer insulating layer; 
 forming a source and a drain of the first thin film transistor and a gate line on a side of the first interlayer insulating layer distal to the base substrate; wherein the source and the drain of the first thin film transistor are electrically connected to the active layer through the source contact via and the drain contact via, respectively; and the gate line is electrically connected to the second gate through the first connection via, 
 wherein the method further comprises forming a second connection via penetrating through the first interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer while forming the source contact via, the drain contact via, and the first connection via penetrating through the first interlayer insulating layer; and 
 the gate line is electrically connected to the first gate to receive a gate signal through the second connection via. 
 
     
     
       11. The method for manufacturing a display substrate of  claim 10 , wherein the step of sequentially forming a first semiconductor material layer, a second gate insulating material layer and a second gate metal layer on a side of the first gate insulating layer distal to the base substrate, and forming a pattern comprising an active layer of the first thin film transistor and a pattern comprising a second gate insulating layer and a second gate of the first thin film transistor comprises steps of:
 sequentially depositing the first semiconductor material layer, the second gate insulating material layer and the second gate metal layer on a side of the first gate insulating layer distal to the base substrate; 
 forming the pattern comprising the second gate insulating layer and the second gate of the first thin film transistor through a patterning process; and 
 coating photoresist on a side of the second gate of the first thin film transistor distal to the base substrate, and forming the pattern comprising the active layer of the first thin film transistor through a patterning process. 
 
     
     
       12. The method for manufacturing a display substrate of  claim 10 , wherein a material of the active layer of the first thin film transistor comprises oxide semiconductor. 
     
     
       13. The method for manufacturing a display substrate of  claim 12 , further comprising forming a low temperature polycrystalline silicon thin film transistor on the base substrate,
 wherein the low temperature polycrystalline silicon thin film transistor comprises a third gate; and 
 the third gate, the first gate and the second gate are sequentially arranged in a direction away from the base substrate. 
 
     
     
       14. The method for manufacturing a display substrate of  claim 10 , wherein
 a depth of the first connection via is smaller than a depth of the source contact via and the drain contact via. 
 
     
     
       15. The method for manufacturing a display substrate of  claim 14 , wherein a depth of the second connection via is larger than the depth of the source contact via and the drain contact via. 
     
     
       16. The method for manufacturing a display substrate of  claim 14 , wherein the source contact via, a channel region of the active layer, and the drain contact via are arranged along a first direction;
 the first connection via and the second connection via are arranged along a second direction; and 
 the first direction crosses the second direction. 
 
     
     
       17. The method for manufacturing a display substrate of  claim 16 , wherein an area of an orthographic projection of the second gate on the base substrate is smaller than that of the active layer. 
     
     
       18. The method for manufacturing a display substrate of  claim 16 , wherein the gate line comprises a first part which is a strip extending along the second direction.

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