Semiconductor memory device and method for fabricating the same

Abstract

A semiconductor memory device comprises a substrate, first and second lower electrode groups on the substrate and including a plurality of first and second lower electrodes, respectively, and first and second support patterns on side walls of and connecting each of the first and second lower electrodes, respectively. The first lower electrodes include a first center lower electrode arranged within a hexagonal shape defined by first edge lower electrodes. The second lower electrodes include a second center lower electrode arranged within a hexagonal shape defined by second edge lower electrodes. The first center lower electrode is spaced apart from each of the first edge lower electrodes in different first to third directions. The first support pattern is immediately adjacent to the second support pattern. The first center lower electrode is spaced apart from the second center lower electrode in a fourth direction different from the first to third directions.

What is claimed is: 
     
       1. A method for fabricating a semiconductor memory device, the method comprising:
 providing a substrate including a first region and a second region, wherein the second region extends along a boundary of the first region; 
 forming a plurality of word lines in the substrate; 
 forming a plurality of buried contacts on the substrate; 
 forming a plurality of landing pads on the plurality of buried contacts, and connected to the buried contacts; 
 forming a plurality of pre-support patterns between the plurality of landing pads; 
 forming a plurality of lower electrodes on the plurality of landing pads, and connected to the landing pads; 
 forming a first mask pattern on the first region of the substrate; 
 removing at least a portion of the plurality of pre-support patterns to form a plurality of support patterns; 
 forming a capacitive dielectric film on the plurality of lower electrodes; and 
 forming an upper electrode on the capacitive dielectric film, 
 wherein the plurality of lower electrodes include a first lower electrode group, 
 wherein the first lower electrode group comprises six first edge lower electrodes arranged at respective vertices of a hexagonal shape, and one first center lower electrode that is centrally positioned within the hexagonal shape, and 
 wherein the first mask pattern completely overlaps with the first center lower electrode in a vertical direction perpendicular to an upper surface of the substrate. 
 
     
     
       2. The method of  claim 1 , wherein the first mask pattern has a circle shape in a plan view. 
     
     
       3. The method of  claim 1 , wherein the first mask pattern exposes at least a portion of each of the first edge lower electrodes in the vertical direction. 
     
     
       4. The method of  claim 1 , wherein the first mask pattern is not formed on the second region. 
     
     
       5. The method of  claim 1 , wherein the each of the support patterns comprise a lower support pattern, and an upper support pattern on the lower support pattern, and
 wherein the lower support pattern is spaced apart from the upper support pattern in the vertical direction. 
 
     
     
       6. The method of  claim 5 , wherein an upper surface of the upper support pattern and an upper surface of the lower electrodes are substantially coplanar. 
     
     
       7. The method of  claim 1 , wherein the plurality of lower electrodes include a second lower electrode group, and
 wherein the second lower electrode group comprises six second edge lower electrodes arranged at respective vertices of a hexagonal shape, and one second center lower electrode that is centrally positioned within the hexagonal shape. 
 
     
     
       8. The method of  claim 7 , further comprising forming a second mask pattern on the first region of the substrate,
 wherein the second mask pattern completely overlaps with the second center lower electrode in the vertical direction. 
 
     
     
       9. A method for fabricating a semiconductor memory device, the method comprising:
 providing a substrate; 
 forming a plurality of word lines in the substrate; 
 forming a plurality of landing pads on the substrate; 
 forming a first lower electrode group on the plurality of landing pads, wherein the first lower electrode group comprises six first edge lower electrodes arranged at respective vertices of a hexagonal shape and free of electrodes between the respective vertices, and one first center lower electrode that is centrally positioned within the hexagonal shape; 
 forming a second lower electrode group on the plurality of landing pads, wherein the second lower electrode group comprises six second edge lower electrodes arranged at respective vertices of a hexagonal shape and free of electrodes between the respective vertices, and one second center lower electrode that is centrally positioned within the hexagonal shape; 
 forming a first mask pattern on the first lower electrode group; 
 forming a second mask pattern on the second lower electrode group; 
 forming a plurality of first support patterns between the first center lower electrode and each of the first edge lower electrodes; 
 forming a plurality of second support patterns between the second center lower electrode and each of the second edge lower electrodes; 
 forming a capacitive dielectric film on a plurality of lower electrodes including the first and second lower electrode groups; and 
 forming an upper electrode on the capacitive dielectric film, 
 wherein the first mask pattern completely overlaps with the first center lower electrode in a vertical direction perpendicular to an upper surface of the substrate, 
 wherein the second mask pattern completely overlaps with the second center lower electrode in the vertical direction, 
 wherein the first center lower electrode is spaced apart from each of the first edge lower electrodes, without electrodes therebetween, in first, second, and third directions that are different from each other, and 
 wherein the first center lower electrode is spaced apart from the second center lower electrode in a fourth direction that is different from the first, second, and third directions. 
 
     
     
       10. The method of  claim 9 , wherein one of the first support patterns is immediately adjacent to one of the second support patterns. 
     
     
       11. The method of  claim 9 , further comprising:
 forming a third lower electrode group on the plurality of landing pads, wherein the third lower electrode group comprises six third edge lower electrodes arranged at respective vertices of a hexagonal shape, and one third center lower electrode that is centrally positioned within the hexagonal shape; and 
 forming a third mask pattern on the third lower electrode group, 
 wherein the third mask pattern completely overlaps with the third center lower electrode in the vertical direction. 
 
     
     
       12. The method of  claim 11 , further comprising forming a plurality of third support patterns between the third center lower electrode and each of the third edge lower electrodes,
 wherein one of the third support pattern is immediately adjacent to ones of the first and second support patterns, and 
 wherein the third center lower electrode is spaced apart from the first center lower electrode in a fifth direction different from the first, second, third, and fourth directions. 
 
     
     
       13. The method of  claim 12 , wherein the third center lower electrode is spaced apart from the second center lower electrode in a sixth direction different from the first, second, third, fourth, and fifth directions. 
     
     
       14. The method of  claim 12 , wherein respective distances between the first and second center lower electrodes, between the second and third center lower electrodes, and between the first and third center lower electrodes are the same. 
     
     
       15. The method of  claim 9 , wherein the each of the first support patterns comprise a lower support pattern, and an upper support pattern on the lower support pattern, and
 wherein the lower support pattern is spaced apart from the upper support pattern in the vertical direction. 
 
     
     
       16. The method of  claim 15 , wherein an upper surface of the upper support pattern and an upper surface of the first center lower electrode are substantially coplanar. 
     
     
       17. A method for fabricating a semiconductor memory device, the method comprising:
 providing a substrate comprising a cell region, wherein the cell region comprises a first region and a second region along a boundary of the first region; 
 forming a plurality of word lines in the cell region of the substrate; 
 forming a plurality of support patterns on the first region of the cell region and spaced apart from each other; 
 forming a dummy support pattern extending along the second region of the cell region, wherein the first region of the cell region is free of the dummy support pattern; 
 forming a plurality of lower electrodes on the first region of the cell region, wherein respective subsets of the lower electrodes are connected by each of the support patterns; and 
 forming a plurality of dummy lower electrodes on the second region of the cell region of the substrate and connected by the dummy support pattern, 
 wherein the support patterns are arranged in a honey-comb structure, and 
 wherein the respective subsets of the lower electrodes consist of six edge lower electrodes arranged along a periphery of each of the support patterns at respective vertices of a hexagonal shape and free of electrodes between the respective vertices, and one center lower electrode that is centrally positioned within the periphery, wherein respective distances between the center lower electrode and each of the edge lower electrodes are the same. 
 
     
     
       18. The method of  claim 17 , wherein a part of the dummy lower electrodes are arranged along the boundary between the first region of the cell region and the second region of the cell region. 
     
     
       19. The method of  claim 17 , wherein the lower electrodes are not in contact with the dummy support pattern. 
     
     
       20. The method of  claim 17 , wherein the center lower electrode is centrally positioned within the hexagonal shape without electrodes between the center lower electrode and the edge lower electrodes.