Socketless or flush mount QFN (quad flat no lead) test board, fixture, and method

Abstract

An apparatus comprises a toggle member, a plurality of pogo pins, and a test board in operable communication with the toggle member. The pogo pins are coupled to the toggle member to move along a first axis when the toggle member moves along the first axis. Each pogo pin includes a plunger that moves within the pogo pin along the first axis. The pogo pins and respective plungers contact a top surface of the DUT when the DUT is coupled to the test board and positioned so that a conductor on its outer surface is aligns to and contacts a conductive region of the test board. Movement of the toggle member along the first axis translates to the plungers, applying a pressure sufficient to the top surface of the DUT to ensure flushmount electrical contact between the conductor of the DUT and the conductive region.

What is claimed is: 
     
       1. A method of testing an integrated circuit with testing apparatus, the method comprising:
 providing a test fixture comprising a toggle member configured for movement along a first axis; 
 fixedly coupling a plurality of pogo pins to the toggle member in a predetermined orientation, wherein the plurality of pogo pins are configured for movement along the first axis when the toggle member is moved, wherein each respective pogo pin includes a respective plunger, from a plurality of plungers, the respective plunger configured to move within the pogo pin along the first axis; 
 providing a test board in operable communication with the toggle member, the test board configured to have a first region for receiving a device under test (DUT), the test board having formed thereon, within the first region, at least one conductive region configured to substantially align with a corresponding conductor disposed on an outer surface of a device under test; 
 configuring an arrangement of the plurality of pogo pins and respective plungers to make contact with a top surface of the DUT when the DUT is positioned to be aligned to and disposed on the first region of the test board; and 
 configuring the testing apparatus so that movement of the toggle member along a first axis translates to at least a portion of the plurality of plungers applying a pressure sufficient to the top surface of the DUT to ensure a flushmount electrical contact between the corresponding conductor of the DUT and the conductive region of the test board; 
 providing an integrated circuit (IC), the IC having a first surface with a plurality of conductors disposed thereon, wherein the first surface has a first coplanarity; 
 performing a hot solder dip (HSD) process on the IC to coat the plurality of conductors with a first thickness of solder coating, to create a dipped IC; 
 burnishing the first thickness of solder coating to a second coplanarity, wherein the second coplanarity is more planar than the first coplanarity, to create a dipped burnished IC; and 
 configuring the dipped burnished IC as the DUT within the test fixture. 
 
     
     
       2. The method of  claim 1 , further comprising configuring the testing apparatus for applying an electrical signal to the conductive region of the test board when the DUT is in flushmount electrical contact with the test board, wherein the flushmount electrical contact is configured to enable the electrical signal to travel from the conductive region of the test board to the corresponding conductor of the DUT. 
     
     
       3. The method of  claim 1 , further comprising configuring the plurality of plungers to apply a distributed pressure. 
     
     
       4. The method of  claim 1  wherein the top surface of the DUT has at least a first region that is supported underneath the top surface and a second region that is not supported under the top surface, and wherein the predetermined orientation of the pogo pins is configured to apply the pressure to the top surface of the DUT only within the first region that is supported. 
     
     
       5. The method of  claim 1 , further comprising configuring the arrangement of the pogo pins and plungers to compensate for at least a portion of variations in coplanarity in at least one of the test board and the DUT. 
     
     
       6. The method of  claim 1  further comprising providing for each respective pogo pin a respective contact tip configured to distribute pressure and minimize damage to the top surface of the DUT when the toggle member is moved. 
     
     
       7. The method of  claim 1 , further comprising:
 disposing the DUT adjacent to the first region of the test board; 
 applying a force to the toggle member sufficient to ensure that the DUT is in flushmount electrical contact with the test board; and 
 applying an electrical signal to the conductive region of the test board, wherein the flushmount electrical contact is configured to enable the electrical signal to travel from the conductive region of the test board to the corresponding conductor of the DUT, wherein the electrical signal is configured to test the DUT.