Memory system determining a degraded word line based on fail bit count and operating method thereof

Abstract

A memory system and an operating method thereof perform word line verification by deactivating each of a plurality of word lines at the same time as initiating a bit line equalization, determine a fail bit count for each word line according to a number of bit flips that occurred during the word line verification, and determine a degraded word line on the basis of the fail bit counts of the plurality of word lines.

What is claimed is: 
     
       1. A method for operating a memory system, comprising:
 performing, in a memory cell array in which a plurality of word lines and a plurality of bit lines intersect with each other, a word line verification by deactivating each of the plurality of word lines and at the same time performing a bit line equalization; 
 determining a fail bit count for each of the plurality of word lines according to a number of bit flips that occurred in memory cells corresponding with that word line during the word line verification; and 
 determining a degraded word line on the basis of fail bit counts of the plurality of word lines, 
 wherein determining the degraded word line comprises:
 determining whether a second word line selected from among the plurality of word lines satisfies a first condition, the first condition being satisfied for a word line when a fail bit count of that word line is larger than a first threshold count; 
 determining whether the second word line satisfies a second condition, the second condition being satisfied for a word line when the fail bit count of that word line is larger than a sum of a second threshold count and a maximum fail bit count between fail bit counts of word lines adjacent to that word line; and 
 determining whether the second word line is the degraded word according to whether the second word line satisfies both the first and second condition. 
 
 
     
     
       2. The method according to  claim 1 , further comprising:
 outputting degraded word line information including an address of the degraded word line, a fail bit count of the degraded word line and a difference between the fail bit count of the degraded word line and a fail bit count of each of one or more word lines adjacent to the degraded word line. 
 
     
     
       3. The method according to  claim 1 , wherein the performing of the word line verification comprises:
 writing a preset pattern to memory cells corresponding to a first word line selected among the plurality of word lines; 
 reading data from the memory cells corresponding to the first word line; and 
 comparing the preset pattern and the data read from the memory cells. 
 
     
     
       4. The method according to  claim 3 , wherein the writing of the preset pattern comprises:
 precharging the plurality of bit lines; 
 activating the first word line; 
 inputting the preset pattern to the memory cells, corresponding to the first word line, through the plurality of bit lines; and 
 precharging the plurality of bit lines by deactivating the first word line and at the same time performing the bit line equalization. 
 
     
     
       5. The method according to  claim 3 , wherein the reading of the data from the memory cells comprises:
 precharging the plurality of bit lines; 
 activating the first word line; 
 outputting data stored in the memory cells corresponding to the first word line on the basis of change amounts in levels of the plurality of bit lines; and 
 precharging the plurality of bit lines by deactivating the first word line and at the same time performing the bit line equalization. 
 
     
     
       6. The method according to  claim 1 , wherein the first threshold count is one-half of the number of bit lines which intersect with the second word line. 
     
     
       7. The method according to  claim 1 , wherein the second threshold count is one-fourth of the number of bit lines which intersect with the second word line. 
     
     
       8. The method according to  claim 1 , wherein, when the second word line and a third word line selected from among the plurality of word lines both satisfy the first condition and the second condition, a fail bit count of the second word line is larger than a fail bit count of the third word line and a difference between a maximum fail bit count between fail bit counts of word lines adjacent to the second word line and the fail bit count of the second word line is larger than a difference between a maximum fail bit count between fail bit counts of word lines adjacent to the third word line and the fail bit count of the third word line, the second word line is determined as the degraded word line. 
     
     
       9. A memory system comprising:
 a memory device including a plurality of word lines, a plurality of bit lines, and a memory cell array in which the plurality of word lines and the plurality of bit lines intersect with each other; and 
 a memory controller configured to: 
 perform a word line verification on each of the plurality of word lines by deactivating each of the plurality of word lines and at the same time performing a bit line equalization, 
 determine a fail bit count for each of the plurality of word lines according to a number of bit flips that occurred in memory cells corresponding with that word line during the word line verification, and 
 determine a degraded word line on the basis of fail bit counts of the plurality of word lines, 
 wherein the memory controller determining the degraded word line comprises:
 determining whether a second word line selected from among the plurality of word lines satisfies a first condition, the first condition being satisfied for a word line when a fail bit count of that word line is larger than a first threshold count; 
 determining whether the second word line satisfies a second condition, the second condition being satisfied for a word line when the fail bit count of that word line is larger than a sum of a second threshold count and a maximum fail bit count between fail bit counts of word lines adjacent to that word line; and 
 determining whether the second word line is the degraded word according to whether the second word line satisfies both the first and second condition. 
 
 
     
     
       10. The memory system according to  claim 9 , wherein the memory controller outputs degraded word line information including an address of the degraded word line, a fail bit count of the degraded word line and a difference between the fail bit count of the degraded word line and a fail bit count of each of one or more word lines adjacent to the degraded word line, on the basis of determination of the degraded word line. 
     
     
       11. The memory system according to  claim 9 , wherein the memory controller writes a preset pattern to memory cells corresponding to a first word line selected among the plurality of word lines, reads data from the memory cells corresponding to the first word line, and compares the preset pattern and the data read from the memory cells. 
     
     
       12. The memory system according to  claim 11 , wherein the memory device precharges the plurality of bit lines, activates the first word line, inputs the preset pattern to the memory cells corresponding to the first word line through the plurality of bit lines, and precharges the plurality of bit lines by deactivating the first word line and at the same time performing the bit line equalization. 
     
     
       13. The memory system according to  claim 11 , wherein the memory device precharges the plurality of bit lines, activates the first word line, outputs data stored in the memory cells corresponding to the first word line on the basis of change amounts in levels of the plurality of bit lines, and precharges the plurality of bit lines by deactivating the first word line and at the same time performing the bit line equalization. 
     
     
       14. The memory system according to  claim 9 , wherein the first threshold count is one-half of the number of bit lines which intersect with the second word line. 
     
     
       15. The memory system according to  claim 9 , wherein the second threshold count is one-quarter of the number of bit lines which intersect with the second word line. 
     
     
       16. The memory system according to  claim 9 , wherein, when the second word line and a third word line selected from among the plurality of word lines both satisfy the first condition and the second condition, a fail bit count of the second word line is larger than a fail bit count of the third word line and a difference between a maximum fail bit count between fail bit counts of word lines adjacent to the second word line and the fail bit count of the second word line is larger than a difference between a maximum fail bit count between fail bit counts of word lines adjacent to the third word line and the fail bit count of the third word line, the memory controller determines the second word line as a degraded word line.