US12273108B2ActiveUtilityA1
Apparatus and method for expanding round keys during data encryption
Est. expiryMar 20, 2043(~16.7 yrs left)· nominal 20-yr term from priority
H03K 19/1737H03K 19/17728H03K 19/21H04L 2209/122H03K 19/17768H04L 9/0631
46
PatentIndex Score
0
Cited by
32
References
20
Claims
Abstract
The invention introduces an apparatus and a method for expanding round keys during data encryption. The method includes: configuring a word-processing circuitry to operate in a first mode to calculate a first intermediate calculation result corresponding to an even-number round key according to a last double word of a 0 th double word to a 7 th double word in each even-number clock cycle starting from a 2 nd clock cycle; and configuring the word-processing circuitry to operate in a second mode to calculate a second intermediate calculation result corresponding to an odd-number round key according to the last double word of the 0 th double word to the 7 th double word in each odd-number clock cycle starting from a 3 rd clock cycle. In the first mode, a first data path is formed in the word-processing circuitry, which includes a word split circuitry, a rotate-word circuitry, a substitute-word circuitry, a round-constant circuitry and a word concatenation circuitry. In the second mode, a second data path is formed in the word-processing circuitry, which includes the word split circuitry, the substitute-word circuitry and the word concatenation circuitry.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. An apparatus for expanding round keys during data encryption, comprising:
a register, comprising components arranged operably to store eight double words, wherein outputs of components for storing a 4 th double word to a 7 th double word are coupled to inputs of components for storing a 0 th double word to a 3 rd double words, respectively; and
a word-processing circuitry, coupled to an output of a component for storing a last double word in the register, arranged operably to: operate in a first mode and a second mode alternately; in the first mode, calculate a first intermediate calculation result corresponding to an even-number round key according to the last double word; and in the second mode, calculate a second intermediate calculation result corresponding to an odd-number round key according to the last double word;
first XOR gates, coupled to an output of a component for storing the 0 th double word in the register and the output of the word-processing circuitry, arranged operably to: perform a first bitwise XOR operation on the 0 th double word and the output of the word-processing circuitry; and output a first calculation result to the component for storing the 4 th double word in the register;
second XOR gates, coupled to an output of a component for storing the 1 st double word in the register and an output of the first XOR gates, arranged operably to: perform a second bitwise XOR operation on the 1 st double word and the output of the first XOR gates; and output a second calculation result to the component for storing the 5 th double word in the register;
third XOR gates, coupled to an output of a component for storing the 2 nd double word in the register and an output of the second XOR gates, arranged operably to: perform a third bitwise XOR operation on the 2 nd double word and the output of the second XOR gates; and output a third calculation result to the component for storing the 6 th double word in the register; and
fourth XOR gates, coupled to an output of a component for storing the 3 rd double word in the register and an output of the third XOR gates, arranged operably to: perform a fourth bitwise XOR operation on the 3 rd double word and the output of the third XOR gates; and output a fourth calculation result to the component for storing the 7 th double word in the register.
2. The apparatus of claim 1 , wherein the 0 th double word to the 3 rd double word form a first round key, the 4 th double word to the 7 th double word form a second round key, the first round key is 128 bits and the second round key is 128 bits.
3. The apparatus of claim 1 , wherein the first to the fourth calculation results are expressed by the following formulae:
DW
4
=
W
tmp
⊕
W
0
,
0
DW
5
=
W
tmp
⊕
W
0
,
0
⊕
W
0
,
1
DW
6
=
W
tmp
⊕
W
0
,
0
⊕
W
0
,
1
⊕
W
0
,
2
DW
7
=
W
tmp
⊕
W
0
,
0
⊕
W
0
,
1
⊕
W
0
,
2
⊕
W
0
,
3
wherein DW 4 represents the first calculation result, DW 5 represents the second calculation result, DW 6 represents the third calculation result, DW 7 represents the fourth calculation result, Wtmp represents an intermediate calculation result outputted from the word-processing circuitry, W i,0 represents the 0 th word of an i th round key, W i,1 represents the 1 st word of the i th round key, W i,2 represents the 2 nd word of the i th round key, W i,3 represents the 3 rd word of the i th round key, i is an integer ranging from 1 to 12.
4. The apparatus of claim 1 , wherein the word-processing circuitry comprises:
a word split circuitry, coupled to the output of the component for storing the last double word, arranged operably to divide the last double word into four first bytes;
a rotate-word circuitry, coupled to an output of the word split circuitry, arranged operably to circular left shift the four first bytes received from the word split circuitry by one byte to become four second bytes;
a first multiplexer (MUX), comprising a first input terminal, a second input terminal and a first output terminal, wherein the first input terminal is coupled to an output of the rotate-word circuitry and the second input terminal is coupled to an output of the word split circuitry;
a substitute-word circuitry, coupled to first output terminal of the first MUX, arranged operably to convert each of the four first bytes or the four second bytes received from the first output terminal of the first MUX into a third byte according to a lookup table;
a round-constant circuitry, coupled to an output of the substitute-word circuitry, arranged operably to perform a bitwise XOR operation on each third byte and a constant to generate a fourth byte;
a second MUX, comprising a third input terminal, a fourth input terminal and a second output terminal, wherein the third input terminal is coupled to an output of the round-constant circuitry and the fourth input terminal is coupled to the output of the substitute-word circuitry; and
a word concatenation circuitry, coupled to the second output terminal of the second MUX, arranged operably to combine the four fourth bytes received from the second terminal of the second MUX to generate the first intermediate calculation result; or combine the four third bytes received from the second terminal of the second MUX to generate the second intermediate calculation result.
5. The apparatus of claim 4 , comprising:
a controller, coupled to the first MUX and the second MUX, arranged operably to: issue a first mode selection signal to the first MUX to connect the first input terminal to the first output terminal, and issue the first mode selection signal to the second MUX to connect the third input terminal to the second output terminal in each even-number clock cycle starting from a 2 nd clock cycle; and issue a second mode selection signal to the second MUX to connect the second input terminal to the first output terminal, and issue the second mode selection signal to the second MUX to connect the fourth input terminal to the second output terminal in each odd-number clock cycle starting from a 3 rd clock cycle.
6. The apparatus of claim 4 , wherein the word-processing circuitry comprises:
a demultiplexer (DEMUX), comprising a fifth input terminal, a third output terminal and a fourth output terminal, wherein the fifth input terminal is coupled to the output of the substitute-word circuitry;
a first parity compensation circuitry, coupled to the third output terminal, arranged operably to generate a first across-word parity 9-bit corresponding to the odd-number round key according to the four third bytes; and
a second parity compensation circuitry, coupled to the fourth output terminal, arranged operably to generate a second across-word parity 9-bit corresponding to the even-number round key according to the four third bytes.
7. The apparatus of claim 6 , comprising:
a controller, coupled to the DEMUX, arranged operably to: issue a first mode selection signal to the DEMUX to connect the fifth input terminal to the third output terminal in each even-number clock cycle starting from a 2 nd clock cycle; and issue a second mode selection signal to the DEMUX to connect the fifth input terminal to the fourth output terminal in each odd-number clock cycle starting from a 3 rd clock cycle.
8. The apparatus of claim 4 , wherein the substitute-word circuitry comprises four enhanced search circuitry and each enhanced search circuitry comprises:
a search circuitry, arranged operably to convert the first value of any of the four first bytes and the four second bytes into the second value of a K-bit according to an 8-to-K lookup table, wherein K is an integer ranging from 10 to 15 and the second value comprises (K minus 8) bits of a Hamming parity; and
a substitution check circuitry, coupled to the search circuitry, arranged operably to employ check formulae corresponding to the 8-to-K lookup table to determine whether an error is occurred during a conversion of the first value of the one byte into the second value of the K-bit, and output an error signal when finding the error, wherein a total amount of the formulae is K minus 8.
9. The apparatus of claim 8 , wherein most-significant 8 bits of each cell in the 8-to-K lookup table is established by a formula as follows:
SB
i
=
Affine
(
(
i
)
-
1
)
SB i represents an output result of a value i, Affine( ) represents an Affine transformation function, and i is an integer ranging from 0 to 127.
10. The apparatus of claim 8 , wherein K is 14.
11. The apparatus of claim 10 , wherein the substitution check circuitry is arranged operably to use following 6 check formulae to analyze 6 bits of the Hamming parity according to a most-significant byte of the second value:
Hm
5
==
S
7
′
(
out
)
+
S
6
′
(
out
)
+
S
5
′
(
out
)
+
S
4
′
(
out
)
+
S
3
′
(
out
)
+
S
2
′
(
out
)
+
S
1
′
(
out
)
+
S
0
′
(
out
)
Hm
4
==
S
7
′
(
out
)
+
S
4
′
(
out
)
+
S
0
′
(
out
)
Hm
3
==
S
6
′
(
out
)
+
S
5
′
(
out
)
+
S
1
′
(
out
)
+
S
0
′
(
out
)
Hm
2
==
S
4
′
(
out
)
+
S
2
′
(
out
)
+
S
1
′
(
out
)
Hm
1
==
S
5
′
(
out
)
+
S
3
′
(
out
)
+
S
2
′
(
out
)
Hm
0
==
S
7
′
(
out
)
+
S
6
′
(
out
)
+
S
3
′
(
out
)
Hm 5 to Hm 0 represent a 5 th bit to a 0 bit of the Hamming parity, respectively, and S′ (out) 7 to S′ (out) 0 represent a 7 th bit to a 0 th bit of the most-significant byte of the second value, respectively, and
wherein the substitution check circuitry is arranged operably to output the error signal when any one or more of the 6 check formulae are invalid.
12. The apparatus of claim 10 , wherein the substitution check circuitry is arranged operably to use following 6 check formulae to analyze 6 bits of the Hamming parity according to a most-significant byte of the second value:
Hm
5
==
S
7
′
(
out
)
+
S
6
′
(
out
)
+
S
5
′
(
out
)
+
S
4
′
(
out
)
+
S
3
′
(
out
)
+
S
2
′
(
out
)
+
S
1
′
(
out
)
+
S
0
′
(
out
)
Hm
4
==
S
7
′
(
out
)
+
S
4
′
(
out
)
+
S
0
′
(
out
)
Hm
3
==
S
5
′
(
out
)
+
S
2
′
(
out
)
+
S
1
′
(
out
)
+
S
0
′
(
out
)
Hm
2
==
S
6
′
(
out
)
+
S
4
′
(
out
)
+
S
1
′
(
out
)
Hm
1
==
S
6
′
(
out
)
+
S
5
′
(
out
)
+
S
3
′
(
out
)
Hm
0
==
S
7
′
(
out
)
+
S
3
′
(
out
)
+
S
2
′
(
out
)
Hm 5 to Hm 0 represent a 5 th bit to a 0 th bit of the Hamming parity, respectively, and S′ (out) 7 to S′ (out) 0 represent a 7 th bit to a 0 th bit of the most-significant byte of the second value, respectively, and
wherein the substitution check circuitry is arranged operably to output the error signal when any one or more of the 6 check formulae are invalid.
13. The apparatus of claim 4 , wherein the substitute-word circuitry comprises four enhanced search circuitry and each enhanced search circuitry comprises:
a search circuitry, arranged operably to convert the first value of any of the first bytes and the second bytes into the second value according to a lookup table; and
a substitution check circuitry, coupled to the search circuitry, arranged operably to employ check formulae corresponding to the lookup table to determine whether an error is occurred during a conversion of the first value into the second value, and output the error signal when finding the error.
14. The apparatus of claim 13 , wherein the lookup table is established by a formula as follows:
SB
i
=
Affine
(
(
i
)
-
1
)
SB i represents an output result of a value i, Affine( ) represents the Affine transformation function, and i is an integer ranging from 0 to 127.
15. The apparatus of claim 14 , wherein the substitution check circuitry comprises:
a computation circuitry, coupled to the search circuitry, arranged operably to obtain the second value, and calculate Affine(S′ (out) ) −1 to generate a third value, wherein S′ (out) represents the second value, Affine( ) −1 represents an inverse function of Affine transformation;
a multiplier, coupled to the search circuitry and the computation circuitry, arranged operably to multiply the second value by the third value to generate a fourth value; and
a comparator, coupled to the search circuitry and the multiplier, arranged operably to generate a judgment result by implementing logic operations as follows:
err_nl
=
0
,
if
(
S
′
(
mul
)
==
1
)
&&
(
S
′
(
in
)
!=
0
)
&&
(
Affine
(
S
′
(
out
)
)
-
1
!=
0
)
err_nl
=
0
,
if
(
S
′
(
mul
)
==
0
)
&&
(
S
′
(
in
)
==
0
)
&&
(
Affine
(
S
′
(
out
)
)
-
1
==
0
)
err_nl
=
1
,
otherwise
S′ (mul) represents the fourth value, S′ (in) represents the first value, S′ (out) represents the second value, wherein the error is occurred when err_nl=1.
16. A method for expanding round keys during data encryption, performed by a controller, comprising:
configuring a word-processing circuitry to operate in a first mode to calculate a first intermediate calculation result corresponding to an even-number round key according to a last double word of a 0 th double word to a 7 th double word in each even-number clock cycle starting from a 2 nd clock cycle, wherein, in the first mode, a first data path is formed in the word-processing circuitry, which comprises a word split circuitry, a rotate-word circuitry, a substitute-word circuitry, a round-constant circuitry and a word concatenation circuitry; and
configuring the word-processing circuitry to operate in a second mode to calculate a second intermediate calculation result corresponding to an odd-number round key according to the last double word of the 0 th double word to the 7 th double word in each odd-number clock cycle starting from a 3 rd clock cycle, wherein, in the second mode, a second data path is formed in the word-processing circuitry, which comprises the word split circuitry, the substitute-word circuitry and the word concatenation circuitry.
17. The method of claim 16 , wherein the 0 th double word to the 3 rd double word form a first round key, the 4 th double word to the 7 th double word form a second round key, the first round key is 128 bits and the second round key is 128 bits.
18. The method of claim 16 , wherein the word-processing circuitry comprising:
the word split circuitry, arranged operably to divide the last double word into four first bytes;
the rotate-word circuitry, coupled to an output of the word split circuitry, arranged operably to circular left shift the four first bytes received from the word split circuitry by one byte to become four second bytes;
a first multiplexer (MUX), comprising a first input terminal, a second input terminal and a first output terminal, wherein the first input terminal is coupled to an output of the rotate-word circuitry and the second input terminal is coupled to an output of the word split circuitry;
the substitute-word circuitry, coupled to first output terminal of the first MUX, arranged operably to convert each of the four first bytes or the four second bytes received from the first output terminal of the first MUX into a third byte according to a lookup table;
the round-constant circuitry, coupled to an output of the substitute-word circuitry, arranged operably to perform a bitwise XOR operation on each third byte and a constant to generate a fourth byte;
a second MUX, comprising a third input terminal, a fourth input terminal and a second output terminal, wherein the third input terminal is coupled to an output of the round-constant circuitry and the fourth input terminal is coupled to the output of the substitute-word circuitry; and
the word concatenation circuitry, coupled to the second output terminal of the second MUX, arranged operably to combine the four fourth bytes received from the second terminal of the second MUX to generate the first intermediate calculation result; or combine the four third bytes received from the second terminal of the second MUX to generate the second intermediate calculation result.
19. The method of claim 16 , the method comprising:
issuing a first mode selection signal to the first MUX to connect the first input terminal to the first output terminal, and issuing the first mode selection signal to the second MUX to connect the third input terminal to the second output terminal to form the first data path in the word-processing circuitry in each even-number clock cycle starting from the 2 nd clock cycle; and
issuing a second mode selection signal to the second MUX to connect the second input terminal to the first output terminal, and issuing the second mode selection signal to the second MUX to connect the fourth input terminal to the second output terminal to form the second data path in the word-processing circuitry in each odd-number clock cycle starting from the 3 rd clock cycle.
20. The method of claim 16 , wherein the first intermediate calculation result is used to generate the even-number round key and the second intermediate calculation result is used to generate the odd-number round key.Cited by (0)
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