Driver circuit for low voltage differential signaling, LVDS, line driver arrangement for LVDS and method for operating an LVDS driver circuit

Abstract

A driver circuit for low voltage differential signaling, LVDS, includes a phase alignment circuit including an input configured to receive an input signal, a first output configured to provide an internal signal as a function of the input signal, and a second output configured to provide an inverted internal signal, which is the inverted signal of the internal signal, and an output driver circuit coupled to the phase alignment circuit, the output driver circuit including a first input configured to receive the internal signal, a second input configured to receive the inverted internal signal, a first output configured to provide an output signal as a function of the internal signal and a second output configured to provide an inverted output signal which is the inverted signal of the output signal. The phase alignment circuit provides the inverted internal signal with its phase aligned to a phase of the internal signal.

The invention claimed is: 
     
       1. A driver circuit for low voltage differential signaling, LVDS, comprising
 a phase alignment circuit comprising an input configured to receive an input signal, a first output configured to provide an internal signal as a function of the input signal, and a second output configured to provide an inverted internal signal, which is the inverted signal of the internal signal, and 
 an output driver circuit coupled to the phase alignment circuit, the output driver circuit comprising a first input configured to receive the internal signal, a second input configured to receive the inverted internal signal, a first output configured to provide an output signal as a function of the internal signal and a second output configured to provide an inverted output signal which is the inverted signal of the output signal, 
 wherein the phase alignment circuit is configured to provide the inverted internal signal with its phase being aligned to a phase of the internal signal, wherein the phase alignment circuit comprises 
 a first inverter having an input, which is connected to the input of the phase alignment circuit, an output configured to provide an inverted input signal from the input signal, a first inverter supply terminal, which is connected to a supply voltage terminal, and a first inverter reference terminal, which is connected to a reference voltage terminal, 
 a second inverter having an input, which is connected to the output of the first inverter, an output configured to provide the internal signal from the inverted input signal, a second inverter supply terminal, which is connected to the supply voltage terminal via a first switch, and a second inverter reference terminal, which is connected to the reference voltage terminal via a second switch, and 
 a third inverter having an input which is connected to the input of the first inverter and an output configured to provide the inverted internal signal from the input signal, a third inverter supply terminal, which is connected to the second inverter supply terminal of the second inverter and to the supply voltage terminal via a third switch, and a third inverter reference terminal which is connected to the second inverter reference terminal of the second inverter and to the reference voltage terminal via a fourth switch. 
 
     
     
       2. The driver circuit according to  claim 1 ,
 wherein 
 the first switch has a control input which is connected to the output of the second inverter, 
 the second switch has a control input which is connected to the output of the second inverter, 
 the third switch has a control input which is connected to the output of the third inverter, and 
 the fourth switch has a control input which is connected to the output of the third inverter. 
 
     
     
       3. The driver circuit according to  claim 1 ,
 wherein 
 the first inverter comprises a first pair of complementary metal-oxide-semiconductor, MOS, transistors, 
 the second inverter comprises a second pair of complementary MOS transistors, 
 the third inverter comprises a third pair of complementary MOS transistors. 
 
     
     
       4. The driver circuit according to  claim 1 , wherein
 the first switch comprises a MOS transistor with a controlled section connected between the supply voltage terminal and the second inverter supply terminal of the second inverter, 
 the second switch comprises a MOS transistor with a controlled section connected between the reference voltage terminal and the second inverter reference terminal of the second inverter, 
 the third switch comprises a MOS transistor with a controlled section connected between the supply voltage terminal and the third inverter supply terminal of the third inverter, 
 the fourth switch comprises a MOS transistor with a controlled section connected between the reference voltage terminal and the third inverter reference terminal of the third inverter. 
 
     
     
       5. The driver circuit according to  claim 1 ,
 wherein the phase alignment circuit further comprises 
 a first capacitor which is coupled to the first output of the phase alignment circuit and to the reference potential terminal, and 
 a second capacitor which is coupled to the second output of the phase alignment circuit and to the reference potential terminal. 
 
     
     
       6. The driver circuit according to  claim 1 ,
 wherein the input signal comprises a digital signal. 
 
     
     
       7. The driver circuit according to  claim 1 ,
 wherein the output driver circuit is configured to provide the output signal and the inverted output signal using a constant current, wherein a direction of the current represents a logical level of the output signal and the inverted output signal. 
 
     
     
       8. A line driver arrangement for low voltage differential signaling, LVDS, comprising the driver circuit according to  claim 1 , wherein the input signal comprises a voltage signal and the output signal and the inverted output signal represent a differential voltage output signal of the line driver arrangement.